6 research outputs found
Energy Efficient Design for Deep Sub-micron CMOS VLSIs
Over the past decade, low power, energy efficient VLSI design has been the focal point of active research and development. The rapid technology scaling, the growing integration capacity, and the mounting active and leakage power dissipation are contributing to the growing complexity of modern VLSI design. Careful power planning on all design levels is required. This dissertation tackles the low-power, low-energy challenges in deep sub-micron technologies on the architecture and circuit levels.
Voltage scaling is one of the most efficient ways for reducing power and energy. For ultra-low voltage operation, a new circuit technique which allows bulk CMOS circuits to work in the sub-0. 5V supply territory is presented. The threshold voltage of the slow PMOS transistor is controlled dynamically to get a lower threshold voltage during the active mode. Due to the reduced threshold voltage, switching speed becomes faster while active leakage current is increased. A technique to dynamically manage active leakage current is presented. Energy reduction resulting from using the proposed structure is demonstrated through simulations of different circuits with different levels of complexity.
As technology scales, the mounting leakage current and degraded noise immunity impact performance especially that of high performance dynamic circuits. Dual threshold technology shows a good potential for leakage reduction while meeting performance goals. A model for optimally selecting threshold voltages and transistor sizes in wide fan-in dynamic circuits is presented. On the circuit level, a novel circuit level technique which handles the trade-off between noise immunity and energy dissipation for wide fan-in dynamic circuits is presented. Energy efficiency of the proposed wide fan-in dynamic circuit is further enhanced through efficient low voltage operation.
Another direct consequence of technology scaling is the growing impact of interconnect parasitics and process variations on performance. Traditionally, worst case process, parasitics, and environmental conditions are considered. Designing for worst case guarantees a fail-safe operation but requires a large delay and voltage margins. This large margin can be recovered if the design can adapt to the actual silicon conditions. Dynamic voltage scaling is considered a key enabler in reducing such margin. An on-chip process identifier to recover the margin required due to process variations is described. The proposed architecture adjusts supply voltage using a hybrid between the one-time voltage setting and the continuous monitoring modes of operation. The interconnect impact on delay is minimized through a novel adaptive voltage scaling architecture. The proposed system recovers the large delay and voltage margins required by conventional systems by closely tracking the actual critical path at anytime. By tracking the actual critical path, the proposed system is robust and more energy efficient compared to both the conventional open-loop and closed-loop systems
Non-invasive power gating techniques for bursty computation workloads using micro-electro-mechanical relays
PhD ThesisElectrostatically-actuated Micro-Electro-Mechanical/Nano-Electro- Mechanical
(MEM/NEM) relays are promising devices overcoming the
energy-efficiency limitations of CMOS transistors. Many exploratory
research projects are currently under way investigating the mechanical,
electrical and logical characteristics of MEM/NEM relays. One
particular issue that this work addresses is the need for a scalable
and accurate physical model of the MEM/NEM switches that can be
plugged into the standard EDA software.
The existing models are accurate and detailed but they suffer
from the convergence problem. This problem requires finding ad-hoc
workarounds and significantly impacts the designer’s productivity. In
this thesis we propose a new simplified Verilog-AMS model. To test
scalability of the proposed model we cross-checked it against our analysis
of a range of benchmark circuits. Results show that, compared to
standard models, the proposed model is sufficiently accurate with an
average of 6% error and can handle larger designs without divergence.
This thesis also investigates the modelling, designing and optimization
of various MEM/NEM switches using 3D Finite Element Analysis
(FEA) performed by the COMSOL multiphysics simulation tool. An
extensive parametric sweep simulation is performed to study the
energy-latency trade-offs of MEM/NEM relays. To accurately simulate
MEMS/NEMS-based digital circuits, a Verilog-AMS model is
proposed based on the evaluated parameters obtained from the multiphysics
simulation tool. This allows an accurate calibration of the
MEM/NEM relays with a significant reduction in simulation speed
compared to that of 3D FEA exercised on COMSOL tool.
The effectiveness of two power gating approaches in asynchronous
micropipelines is also investigated using MEM/NEM switches and
sleep transistors in reducing idle power dissipation with a particular
target throughput. Sleep transistors are traditionally used to power
gate idle circuits, however, these transistors have fundamental limitations
in their effectiveness. Alternatively, MEM/NEM relays with zero
leakage current can achieve greater energy savings under a certain
data rate and design architecture. An asynchronous FIR filter 4 phase
bundled data handshake protocol is presented. Implementation is
accomplished in 90nm technology node and simulation exercised at
various data rates and design complexities. It was demonstrated that
our proposed approach offers 69% energy improvements at a data rate
1KHz compared to 39% of the previous work.
The current trends for greater heterogeneity in future Systems-on-
Chip (SoC) do not only concern their functionality but also their timing and power aspects. The increasing diversity of timing and power supply
conditions, and associated concurrently operating modes, within
an SoC calls for more efficient power delivery networks (PDN) for
battery operated devices. This is especially important for systems with
mixed duty cycling, where some parts are required to work regularly
with low-throughput while other parts are activated spontaneously,
i.e. in bursts. To improve their reaction time vs energy efficiency, this
work proposes to incorporate a power-switching network based on
MEM relays to switch the SoC power-performance state (PPS) into
an active mode while eliminating the leakage current when it is idle.
Results show that even with today0s large and high pull-in voltages, a
MEM-relay-based power switching network (PSN) can achieve a 1000x
savings in energy compared to its CMOS counterpart for low duty
cycle. A simple case of optimising an on-chip charge pump required
to switch-on the relay has been investigated and its energy-latency
overhead has been evaluated.
Heterogeneous many-core systems are increasingly being employed
in modern embedded platforms for high throughput at low energy cost
considerations. These applications typically exhibit bursty workloads
that provide opportunities to minimize system energy. CMOS-based
power gating circuitry, typically consisting of sleep transistors, is used
as an effective technique for idle energy reduction in such applications.
However, these transistors contribute high leakage current when
driving large capacitive loads, making effective energy minimization
challenging.
This thesis proposes a novel MEMS-based idle energy control approach.
Core to this approach is an integrated sleep mode management
based on the performance-energy states and bursty workloads
indicated by the performance counters. A number of PARSEC benchmark
applications are used as case studies of bursty workloads, including
CPU- and memory- intensive ones. These applications are
exercised on an Exynos 5422 heterogeneous many-core platform, engineered
with a performance counter facilities, showing 55.5% energy
savings compared with an on-demand governor. Furthermore, an extensive
trade-off analysis demonstrates the comparative advantages
of the MEMS-based controller, including zero-leakage current and
non-invasive implementations suitable for commercial off-the-shelf
systems.Higher committee of education development in
Iraq (HCED
Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits
Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the ground-bouncing-noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual lines to the real ground distribution network during the SLEEP to ACTIVE mode transitions. The dependence of ground bouncing noise on the sleep transistor size and temperature is characterized with different power-gating structures. The peak amplitude of ground bouncing noise is reduced by up to 76.62\% with the noise-aware techniques without sacrificing the savings in leakage power consumption as compared with standard MTCMOS circuits in a 90-nm CMOS technology