Layout of compound directed graphs

We present a method for the layout of compound directed graphs that is based on the hierarchical layer layout method. Our method has similarities with the method of Sugiyama and Misue (IEEE Trans. Sys., Man, Cybernetics, 21(4), pp. 876-892, 1991) but gives different results: It uses a global partitioning into layers and tries to produce placements of nodes such that border rectangles can be drawn around the nodes of each subgraph. The method is implemented in the VCG tool

An automated routing method for VLSI with three interconnection layers

Recently, to the extent allowed by the fabricating technology, approaches have been made to develop an automated router for the multi-layer IC layout design. In this thesis, we examine the VLSI routing problem where three layers are available for interconnection;We investigate the routing problem in three stages: global routing, power/ground routing, and channel routing. The global routing for three-interconnection layer model is not much different from that of two-layer madel. We study the global routing problem for two cases: gate array and general cell layout. In our three-layer grid model, power/ground wires keep the direction-per-layer scheme as signal net wires. However, the power/ground routing is further constrained by the width of wires and the layers they are laid on;The channel routing stage of our router is based on directional model where overlaps of horizontal wire segments are allowed. We improve the dogleg method so that it is applicable to the three-layer model and it can handle multi-terminal nets more efficiently. Applying the extensive dogleg method and the three-layer merge algorithm, we not only remove the cyclic vertical constraints graph but also eliminate the effect of the height of long vertical constraints tree to the channel width and thus we reduce the lower bound of the channel width to half of the density of the channel. We expand the applicability of channel router by eliminating some of the limitations assumed in channel routing problems by some existing algorithms. Routability conditions are examined for various cases of channel routing problem;The major result presented in this dissertation is an algorithm for a channel routing problem. Given a rectangular channel with terminals on top and bottom sides, the algorithm will find a three-layer channel routing which minimizes the channel width and the wire length. Experimental results show that our router is close to optimal

Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization

Moving towards an electrified world requires ultra high-density power converters. Electric vehicles, electrified aerospace, data centers, etc. are just a few fields among wide application areas of power electronic systems, where high-density power converters are essential. As a critical part of these power converters, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the emerging MCPM layouts is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with ongoing research toward enhanced capabilities to speed up the optimized MCPM layout design process. This dissertation presents the PowerSynth progression timeline with the methodology updates and corresponding critical results compared to v1.1. The first released version (v1.1) of PowerSynth demonstrated the benefits of layout abstraction, and reduced-order modeling techniques to perform rapid optimization of the MCPM module compared to the traditional, manual, and iterative design approach. However, that version is limited by several key factors: layout representation technique, layout generation algorithms, iterative design-rule-checking (DRC), optimization algorithm candidates, etc. To address these limitations, and enhance PowerSynth’s capabilities, constraint-aware, scalable, and efficient algorithms have been developed and implemented. PowerSynth layout engine has evolved from v1.3 to v2.0 throughout the last five years to incorporate the algorithm updates and generate all 2D/2.5D/3D Manhattan layout solutions. These fundamental changes in the layout generation methodology have also called for updates in the performance modeling techniques and enabled exploring different optimization algorithms. The latest PowerSynth 2 architecture has been implemented to enable electro-thermo-mechanical and reliability optimization on 2D/2.5D/3D MCPM layouts, and set up a path toward cabinet-level optimization. PowerSynth v2.0 computer-aided design (CAD) flow has been hardware-validated through manufacturing and testing of an optimized novel 3D MCPM layout. The flow has shown significant speedup compared to the manual design flow with a comparable optimization result

Engineering management of early stage warship design

Warship Feasibility Studies are highly complex projects. The thesis attempts to highlight the relevant factors inherent within industry and academia and then derives a methodology for managing early stage warship design. The initial data were gathered at the VT shipyard by interviewing key personnel. The collected data are then analysed using the MS Visio flowchart package to create input/output diagrams for all existing areas of work. Identifying explicit and implicit links allows the existing areas of work to be linked and inherent areas to be identified. The resulting connection diagrams are then analysed and compared with existing literature. The analysis results in the creation of several loops depicting the data flow during the assessment phase.Two case studies are carried out to further refine the developed interface model. This model is further improved by carrying out in-depth investigations into previously neglected design factors. A series of algorithms are developed that can be used to determine balanced designs for corvettes and fast attack craft. These algorithms are used to identify factors and events that need extra attention during the design process. Different tools for managing the dataflow across the identified interfaces are researched and a set of control mechanisms is described in more detail. One mechanism, Margins, is further investigated using the developed algorithms in combination with knowledge obtained at VT to determine suitable margin ranges and applications.The results from the interface analysis and interface management studies are combined to derive a management methodology, consisting of a project schedule, a set of functional flowcharts and an accompanying guidance manual. This methodology is tested and validated on a design study. The results from the validation are used to determine any required changes to the methodology. The developed methodology is found to provide an effective tool for managers and designers during the early stages of warship design in a defence environment

A Compiler and Runtime Infrastructure for Automatic Program Distribution

This paper presents the design and the implementation of a compiler and runtime infrastructure for automatic program distribution. We are building a research infrastructure that enables experimentation with various program partitioning and mapping strategies and the study of automatic distribution's effect on resource consumption (e.g., CPU, memory, communication). Since many optimization techniques are faced with conflicting optimization targets (e.g., memory and communication), we believe that it is important to be able to study their interaction. We present a set of techniques that enable flexible resource modeling and program distribution. These are: dependence analysis, weighted graph partitioning, code and communication generation, and profiling. We have developed these ideas in the context of the Java language. We present in detail the design and implementation of each of the techniques as part of our compiler and runtime infrastructure. Then, we evaluate our design and present preliminary experimental data for each component, as well as for the entire system

Graph layout for applications in compiler construction

We address graph visualization from the viewpoint of compiler construction. Most data structures in compilers are large, dense graphs such as annotated control flow graph, syntax trees, dependency graphs. Our main focus is the animation and interactive exploration of these graphs. Fast layout heuristics and powerful browsing methods are needed. We give a survey of layout heuristics for general directed and undirected graphs and present the browsing facilities that help to manage large structured graph

VCG - visualization of compiler graphs

The VCG tool allows the visualization of graphs that occur typically as data structures in programs. We describe the design concepts of the tool, its specification language and its usage. The tool supports the partitioning of edges and nodes into edge classes and nested subgraphs, the folding of regions, and the management of priorities of edges

VCG - visualization of compiler graphs

The VCG tool allows the visualization of graphs that occur typically as data structures in programs. We describe the design concepts of the tool, its specification language and its usage. The tool supports the partitioning of edges and nodes into edge classes and nested subgraphs, the folding of regions, and the management of priorities of edges