Développement et optimisation au niveau des matériaux des mémoires résistives à changement de valence pour le calcul-en-mémoire

Le développement des technologies de mémoires résistives non-volatiles a permis d’explorer de nouvelles approches de calcul plus performantes que celles basées sur l’architecture conventionnelle de von Neumann. Notamment, l’approche de calcul-en-mémoire propose une solution à l’étranglement de von Neumann en poussant l’idée de concevoir une architecture où il n’y a pas de séparation physique entre le processeur et la mémoire. Cette approche repose sur les propriétés uniques des mémoires résistives (mémristors) lorsqu’elles sont agencées en réseaux crossbar, où les fonctions de sommation et de multiplication s’implémentent de manière naturelle. De plus, la compatibilité de ces mémoires pour une intégration avec les technologies CMOS conventionnelles offre des capacités agressives de miniaturisation et d’efficacité énergétique. Pour répondre aux exigences de cette intégration, cette thèse a porté d’abord sur le développement du procédé de dépôt du matériau à commutation de résistance (TiO2). L’influence de la concentration de défauts sur les propriétés optiques, structurales et sur la composition chimique du TiO2 a été évaluée. Par la suite, le matériau à commutation de résistance développé a été utilisé pour la fabrication de mémristors de structure TiN/Al2O3/TiO2-x/Ti/TiN/Al. Le procédé de fabrication utilisé est compatible CMOS et s’est basé sur le procédé damascène pour réduire la rugosité de surface des électrodes afin de minimiser la variabilité entre composants (device-to-device variability). Les caractéristiques électriques des mémristors ont été évaluées en quasi-statique ainsi qu’en utilisant des courtes impulsions de tension pour reproduire les conditions réelles d’opération. Les propriétés de commutation résistive analogique ainsi que les fonctions synaptiques de potentialisation et de dépression à long terme ont été démontré. Les mémristors fabriqués peuvent stocker jusqu’à 3 bits avec une stabilité temporelle satisfaisante. Pour réduire les tensions de forming de nos composants, des stratégies combinant la modulation de la concentration de défauts et l’épaisseur du matériau actif ainsi qu’une étape de traitement thermique post-dépôt ont été étudiées. Cette thèse a permis de mettre en oeuvre un procédé de dépôt du matériau à commutation de résistance, d’évaluer les caractéristiques électriques des mémristors et leur potentiel à implémenter les fonctions synaptiques, ainsi que d’explorer des stratégies pertinentes qui peuvent minimiser l’influence des tensions de forming sur l’opération optimale des réseau crossbar

Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors

The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2- and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based RRAM array consumes the least write energy (4.06 pJ/bit) and read energy (188 fJ/bit) when storing 3 bits/cell for 100 nsec write and 1 nsec read access times. Similarly, HfOx-based RRAM array consumes the least write energy (365 fJ/bit) and read energy (173 fJ/bit) when storing 3 bits/cell for 1 nsec write and 200 nsec read access times. On the logic side, we investigate the use of equalization techniques to improve the energy efficiency of digital sequential logic circuits in sub-threshold regime. We first propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors in digital logic designed in sub-threshold regime. This mitigation of timing errors can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path in a combinational logic block using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% (on average) in the sub-threshold regime. Overall, the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. We also propose a tunable adaptive feedback equalizer circuit that can be used with sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in sub-threshold digital logic circuits. For a 64-bit adder designed in 130 nm our proposed approach can reduce the normalized delay variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. In addition, we present detailed energy-performance models of the adaptive feedback equalizer circuit. This work serves as a foundation for the design of robust, energy-efficient digital logic circuits in sub-threshold regime

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor