An audio FIR-DAC in a BCD process for high power Class-D amplifiers

A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at V/sub dd/ = 5 V and the chip area is 2 mm/sup 2/ including the reference diode that can be shared by more channels

An Integrated-Photonics Optical-Frequency Synthesizer

Integrated-photonics microchips now enable a range of advanced functionalities for high-coherence applications such as data transmission, highly optimized physical sensors, and harnessing quantum states, but with cost, efficiency, and portability much beyond tabletop experiments. Through high-volume semiconductor processing built around advanced materials there exists an opportunity for integrated devices to impact applications cutting across disciplines of basic science and technology. Here we show how to synthesize the absolute frequency of a lightwave signal, using integrated photonics to implement lasers, system interconnects, and nonlinear frequency comb generation. The laser frequency output of our synthesizer is programmed by a microwave clock across 4 THz near 1550 nm with 1 Hz resolution and traceability to the SI second. This is accomplished with a heterogeneously integrated III/V-Si tunable laser, which is guided by dual dissipative-Kerr-soliton frequency combs fabricated on silicon chips. Through out-of-loop measurements of the phase-coherent, microwave-to-optical link, we verify that the fractional-frequency instability of the integrated photonics synthesizer matches the $7.0*10^{-13}$ reference-clock instability for a 1 second acquisition, and constrain any synthesis error to $7.7*10^{-15}$ while stepping the synthesizer across the telecommunication C band. Any application of an optical frequency source would be enabled by the precision optical synthesis presented here. Building on the ubiquitous capability in the microwave domain, our results demonstrate a first path to synthesis with integrated photonics, leveraging low-cost, low-power, and compact features that will be critical for its widespread use.Comment: 10 pages, 6 figure

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement

The power mixer array is presented as a novel power generation approach for non-constant envelope signals. It comprises several power mixer units that are dynamically turned on and off to improve the linearity and back-off efficiency. At the circuit level, the power mixer unit can operate as a switching amplifier to achieve high peak power efficiency. Additional circuit level linearization and back-off efficiency improvement techniques are also proposed. To demonstrate the feasibility of this idea, a fully-integrated octave-range CMOS power mixer array is implemented in a 130 nm CMOS process. It is operational between 1.2 GHz and 2.4 GHz and can generate an output power of +31.3 dBm into an external 50 Ω load with a PAE of 42% and a gain compression of only 0.4 dB at 1.8 GHz. It achieves a PAE of 25%, at an average output power of +26.4 dBm, and an EVM of 4.6% with a non-constant-envelope 16 QAM signal. It can also produce arbitrary signal levels down to -70 dBm of output power with the 16 QAM-modulated signal without any RF gain control circuit

Femtosecond resolution timing jitter correction on a TW scale Ti:sapphire laser system for FEL pump-probe experiments

Intense ultrashort pulse lasers are used for fs resolution pumpprobe experiments more and more at large scale facilities, such as free electron lasers (FEL). Measurement of the arrival time of the laser pulses and stabilization to the machine or other sub-systems on the target, is crucial for high time-resolution measurements. In this work we report on a single shot, spectrally resolved, non-collinear cross-correlator with sub-fs resolution. With a feedback applied we keep the output of the TW class Ti:sapphire amplifier chain in time with the seed oscillator to ~3 fs RMS level for several hours. This is well below the typical pulse duration used at FELs and supports fs resolution pump-probe experiments. Short term jitter and long term timing drift measurements are presented. Applicability to other wavelengths and integration into the timing infrastructure of the FEL are also covered to show the full potential of the device

Ultra-Low-Power Wake-up Clock Design for SoC Applications

This thesis studies how to design an ultra-low-power wake-up clock circuit for SoCapplications that essentially consists of a resistor based reference circuit, switched-capacitor branch, an ultra-low-power amplifier, a VCO and a non-overlapping clockphase generator circuit. The circuit is designed in 180-nm CMOS technology usingCAD software for circuit design, layout design, pre and post-layout simulations.At first, a brief study of different clock-generation circuit architectures is made,wherein their merits and de-merits are discussed. This is followed by a study ofan ultra-low-power amplifier, ring-oscillator-based VCO, non-overlapping clockcircuits, the bias generation circuit and the current reference circuit. Additionally,a reference current chopping technique that further improves temperature stabilityis also described. Later, the report discusses the design and simulations of theactual implementation. Analysis of the design with regards to power consumption,temperature stability and layout area are carried out. The circuit operates at8.254kHz consuming 70.4nW with a temperature stability of 7.35ppm/◦C in thetemperature range of -40◦C to 75◦C. The final layout takes an area of 0.153mm2.The final design is analysed for its functionality at various process, voltage andtemperature corners. Future improvements in the current design are also discussedat the end of this report

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply