ASSESSING AND IMPROVING THE RELIABILITY AND SECURITY OF CIRCUITS AFFECTED BY NATURAL AND INTENTIONAL FAULTS

The reliability and security vulnerability of modern electronic systems have emerged as concerns due to the increasing natural and intentional interferences. Radiation of high-energy charged particles generated from space environment or packaging materials on the substrate of integrated circuits results in natural faults. As the technology scales down, factors such as critical charge, voltage supply, and frequency change tremendously that increase the sensitivity of integrated circuits to natural faults even for systems operating at sea level. An attacker is able to simulate the impact of natural faults and compromise the circuit or cause denial of service. Therefore, instead of utilizing different approaches to counteract the effect of natural and intentional faults, a unified countermeasure is introduced. The unified countermeasure thwarts the impact of both reliability and security threats without paying the price of more area overhead, power consumption, and required time. This thesis first proposes a systematic analysis method to assess the probability of natural faults propagating the circuit and eventually being latched. The second part of this work focuses on the methods to thwart the impact of intentional faults in cryptosystems. We exploit a power-based side-channel analysis method to analyze the effect of the existing fault detection methods for natural faults on fault attack. Countermeasures for different security threats on cryptosystems are investigated separately. Furthermore, a new micro-architecture is proposed to thwart the combination of fault attacks and side-channel attacks, reducing the fault bypass rate and slowing down the key retrieval speed. The third contribution of this thesis is a unified countermeasure to thwart the impact of both natural faults and attacks. The unified countermeasure utilizes dynamically alternated multiple generator polynomials for the cyclic redundancy check (CRC) codec to resist the reverse engineering attack

Voltage controlled oscillator with ring structure, with reliability criteria for the effects of radiation

Orientador: Yuzo IanoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Este trabalho apresenta um Oscilador Controlado por Tensão (VCO) com estrutura em anel, usando tecnologia CMOS DARE - UMC 180 nanômetros. O oscilador apresentado será utilizado em um PLL (Phase Locked Loop), que tem como finalidade principal gerar o clock de um sistema digital (baseado no protocolo SpaceWire, o qual é um padrão baseado, em parte, no padrão IEEE 1355 de comunicações, com emprego em links e redes de alta velocidade para uso espaciais, facilitando a interconexão). Este oscilador é composto por uma arquitetura diferencial com um número ímpar de células de atraso. Utilizou-se técnicas de projetos para "endurecer" o circuito, a fim de minimizar os efeitos da radiação ionizante, em especial quanto a ocorrência de efeitos de eventos singulares (SEE) e atingir uma elevada estabilidade no ambiente hostil. A arquitetura apresenta um grau de confiabilidade maior em relação a um oscilador em anel de três estágios (VCO), também apresentado neste trabalho. As simulações realizadas com ambos os osciladores confirmam os resultadosAbstract: This work presents a Voltage Controlled Oscillator (VCO) with ring oscillator structure, using CMOS technology DARE - UMC 180 nanometers. The presented oscillator will be used in a PLL (Phase Locked Loop), whose main purpose is to generate the clock of a digital system (based on the SpaceWire protocol, which is a standard based in part on the IEEE 1355 communications standard, with use in links and high-speed networks for space use, facilitating interconnection). This oscillator consists of a differential architecture with an odd number of delay cells, we used design techniques to harden the circuit in order to minimize the effects of ionizing radiation, in particular the occurrence of single event effects (SEE) and to achieve high stability in the hostile environment. The architecture presents higher reliability than a three-stage ring oscillator, also presented in this work. The simulations performed with both oscillators confirm the resultsMestradoTelecomunicações e TelemáticaMestre em Engenharia Elétric

An advanced Framework for efficient IC optimization based on analytical models engine

En base als reptes sorgits a conseqüència de l'escalat de la tecnologia, la present tesis desenvolupa i analitza un conjunt d'eines orientades a avaluar la sensibilitat a la propagació d'esdeveniments SET en circuits microelectrònics. S'han proposant varies mètriques de propagació de SETs considerant l'impacto dels emmascaraments lògic, elèctric i combinat lògic-elèctric. Aquestes mètriques proporcionen una via d'anàlisi per quantificar tant les regions més susceptibles a propagar SETs com les sortides més susceptibles de rebre'ls. S'ha desenvolupat un conjunt d'algorismes de cerca de camins sensibilitzables altament adaptables a múltiples aplicacions, un sistema lògic especific i diverses tècniques de simplificació de circuits. S'ha demostrat que el retard d'un camí donat depèn dels vectors de sensibilització aplicats a les portes que formen part del mateix, essent aquesta variació de retard comparable a la atribuïble a les variacions paramètriques del proces.En base a los desafíos surgidos a consecuencia del escalado de la tecnología, la presente tesis desarrolla y analiza un conjunto de herramientas orientadas a evaluar la sensibilidad a la propagación de eventos SET en circuitos microelectrónicos. Se han propuesto varias métricas de propagación de SETs considerando el impacto de los enmascaramientos lógico, eléctrico y combinado lógico-eléctrico. Estas métricas proporcionan una vía de análisis para cuantificar tanto las regiones más susceptibles a propagar eventos SET como las salidas más susceptibles a recibirlos. Ha sido desarrollado un conjunto de algoritmos de búsqueda de caminos sensibilizables altamente adaptables a múltiples aplicaciones, un sistema lógico especifico y diversas técnicas de simplificación de circuitos. Se ha demostrado que el retardo de un camino dado depende de los vectores de sensibilización aplicados a las puertas que forman parte del mismo, siendo esta variación de retardo comparable a la atribuible a las variaciones paramétricas del proceso.Based on the challenges arising as a result of technology scaling, this thesis develops and evaluates a complete framework for SET propagation sensitivity. The framework comprises a number of processing tools capable of handling circuits with high complexity in an efficient way. Various SET propagation metrics have been proposed considering the impact of logic, electric and combined logic-electric masking. Such metrics provide a valuable vehicle to grade either in-circuit regions being more susceptible of propagating SETs toward the circuit outputs or circuit outputs more susceptible to produce SET. A quite efficient and customizable true path finding algorithm with a specific logic system has been constructed and its efficacy demonstrated on large benchmark circuits. It has been shown that the delay of a path depends on the sensitization vectors applied to the gates within the path. In some cases, this variation is comparable to the one caused by process parameters variation