318 research outputs found
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an
error-free operation after SEU recovering if the affected configuration bits do
belong to feedback loops of the implemented circuits. In this paper, we a)
provide a netlist-based circuit analysis technique to distinguish so-called
critical configuration bits from essential bits in order to identify
configuration bits which will need also state-restoring actions after a
recovered SEU and which not. Furthermore, b) an alternative classification
approach using fault injection is developed in order to compare both
classification techniques. Moreover, c) we will propose a floorplanning
approach for reducing the effective number of scrubbed frames and d),
experimental results will give evidence that our optimization methodology not
only allows to detect errors earlier but also to minimize the
Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show
that by using our approach, the MTTR for datapath-intensive circuits can be
reduced by up to 48.5% in comparison to standard approaches
Throughput-driven floorplanning with wire pipelining
The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires
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Microarchitecture optimization for timing and layout
In recent years the drive to produce more complex integrated circuits while spending less design time has driven the demand for design automation tools. The search for design automation methods has resulted in the design of numerous behavioral synthesis and logic synthesis tools. This report describes a system that fills the gap between traditional behavioral synthesis and logic synthesis tools. Techniques are introduced for improving the microarchitecture structure and using feedback from lower-level optimization tools to guide design optimizations while attempting to meet user specified area and time constraints. These techniques include the capability for mixing layout styles such as custom layout for random-logic components and bit-slicing for regularly structured components. In this manner the entire design, control logic and datapath, can be optimized at the same time. Further, this paper presents a new methodology for microarchitecture-level optimization that greatly reduces the amount of technology-specific knowledge necessary to perform the optimizations
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs
Modern field programmable gate array(FPGA) can be partially dynamically
reconfigurable with heterogeneous resources distributed on the chip. And
FPGA-based partially dynamically reconfigurable system(FPGA-PDRS) can be used
to accelerate computing and improve computing flexibility.
However, the traditional design of FPGA-PDRS is based on manual design.
Implementing the automation of FPGA-PDRS needs to solve the problems of task
modules partitioning, scheduling, and floorplanning on heterogeneous resources.
Existing works only partly solve problems for the automation process of
FPGA-PDRS or model homogeneous resource for FPGA-PDRS.
To better solve the problems in the automation process of FPGA-PDRS and
narrow the gap between algorithm and application, in this paper, we propose a
complete workflow including three parts, pre-processing to generate the list of
task modules candidate shapes according to the resources requirements,
exploration process to search the solution of task modules partitioning,
scheduling, and floorplanning, and post-optimization to improve the success
rate of floorplan.
Experimental results show that, compared with state-of-the-art work, the
proposed complete workflow can improve performance by 18.7\%, reduce
communication cost by 8.6\%, on average, with improving the resources reuse
rate of the heterogeneous resources on the chip. And based on the solution
generated by the exploration process, the post-optimization can improve the
success rate of the floorplan by 14\%
3D IC optimal layout design. A parallel and distributed topological approach
The task of 3D ICs layout design involves the assembly of millions of
components taking into account many different requirements and constraints such
as topological, wiring or manufacturability ones. It is a NP-hard problem that
requires new non-deterministic and heuristic algorithms. Considering the time
complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is
superior to any other local search method. Nevertheless, it can often miss to
reach a quasi-optimal solution in 3D spaces. The presented approach uses an
original 3D layout graph partitioning heuristics implemented with use of the
extremal optimization method. The goal is to minimize the total wire-length in
the chip. In order to improve the time complexity a parallel and distributed
Java implementation is applied. Inside one Java Virtual Machine separate
optimization algorithms are executed by independent threads. The work may also
be shared among different machines by means of The Java Remote Method
Invocation system.Comment: 26 pages, 9 figure
Efficient Architecture by Effective Floorplanning of Cores in Processors
Hotspots in cores are becoming more prominent all thanks to the increasing clock speed in the market. Core size cannot be increased further. Better technology means reducing the heat or distributing the heat evenly to keep the peak temperature low. One has to find a trade-off between area and cost to make the cores and overall architecture cost effective and heat controlled. Generating floorplans and evaluating them to make the best core is underway. For the current market a trade-off has to be made between area and peak temperature. The floorplan accepted can be built into the desired architecture to gain efficient results
Two-dimensional placement compaction using an evolutionary approach: a study
The placement problem of two-dimensional objects over planar surfaces optimizing
given utility functions is a combinatorial optimization problem. Our main drive is that of
surveying genetic algorithms and hybrid metaheuristics in terms of final positioning area
compaction of the solution. Furthermore, a new hybrid evolutionary approach, combining
a genetic algorithm merged with a non-linear compaction method is introduced and
compared with referenced literature heuristics using both randomly generated instances
and benchmark problems. A wide variety of experiments is made, and the respective
results and discussions are presented. Finally, conclusions are drawn, and future research
is defined
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