Normalizing or not normalizing? An open question for floating-point arithmetic in embedded systems

Emerging embedded applications lack of a specific standard when they require floating-point arithmetic. In this situation they use the IEEE-754 standard or ad hoc variations of it. However, this standard was not designed for this purpose. This paper aims to open a debate to define a new extension of the standard to cover embedded applications. In this work, we only focus on the impact of not performing normalization. We show how eliminating the condition of normalized numbers, implementation costs can be dramatically reduced, at the expense of a moderate loss of accuracy. Several architectures to implement addition and multiplication for non-normalized numbers are proposed and analyzed. We show that a combined architecture (adder-multiplier) can halve the area and power consumption of its counterpart IEEE-754 architecture. This saving comes at the cost of reducing an average of about 10 dBs the Signal-to-Noise Ratio for the tested algorithms. We think these results should encourage researchers to perform further investigation in this issue.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

PERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER

An area-and speed efficient multipliers is proposed in the thesis. the proposed booth and Wallace multipliers shows the tradeoff in the performance evaluation for the fir filter applications. For implementation of fir filter in this paper the adders introduced are carry save adder and carry skip adder. For evaluating the fir filter performance the tested combinations are booth carry save , booth carry skip , Wallace carry save , Wallace carry skip

A general formulation of Bead Models applied to flexible fibers and active filaments at low Reynolds number

This contribution provides a general framework to use Lagrange multipliers for the simulation of low Reynolds number fiber dynamics based on Bead Models (BM). This formalism provides an efficient method to account for kinematic constraints. We illustrate, with several examples, to which extent the proposed formulation offers a flexible and versatile framework for the quantitative modeling of flexible fibers deformation and rotation in shear flow, the dynamics of actuated filaments and the propulsion of active swimmers. Furthermore, a new contact model called Gears Model is proposed and successfully tested. It avoids the use of numerical artifices such as repulsive forces between adjacent beads, a source of numerical difficulties in the temporal integration of previous Bead Models.Comment: 41 pages, 15 figure

Number Systems for Deep Neural Network Architectures: A Survey

Deep neural networks (DNNs) have become an enabling component for a myriad of artificial intelligence applications. DNNs have shown sometimes superior performance, even compared to humans, in cases such as self-driving, health applications, etc. Because of their computational complexity, deploying DNNs in resource-constrained devices still faces many challenges related to computing complexity, energy efficiency, latency, and cost. To this end, several research directions are being pursued by both academia and industry to accelerate and efficiently implement DNNs. One important direction is determining the appropriate data representation for the massive amount of data involved in DNN processing. Using conventional number systems has been found to be sub-optimal for DNNs. Alternatively, a great body of research focuses on exploring suitable number systems. This article aims to provide a comprehensive survey and discussion about alternative number systems for more efficient representations of DNN data. Various number systems (conventional/unconventional) exploited for DNNs are discussed. The impact of these number systems on the performance and hardware design of DNNs is considered. In addition, this paper highlights the challenges associated with each number system and various solutions that are proposed for addressing them. The reader will be able to understand the importance of an efficient number system for DNN, learn about the widely used number systems for DNN, understand the trade-offs between various number systems, and consider various design aspects that affect the impact of number systems on DNN performance. In addition, the recent trends and related research opportunities will be highlightedComment: 28 page

A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits

Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers, as a basic component of many processors and accelerators, have been constantly proposed and studied for decades, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high-level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.Comment: 38 pages, 37 figure

Switchable Genetic Oscillator Operating in Quasi-Stable Mode

Ring topologies of repressing genes have qualitatively different long-term dynamics if the number of genes is odd (they oscillate) or even (they exhibit bistability). However, these attractors may not fully explain the observed behavior in transient and stochastic environments such as the cell. We show here that even repressilators possess quasi-stable, travelling-wave periodic solutions that are reachable, long-lived and robust to parameter changes. These solutions underlie the sustained oscillations observed in even rings in the stochastic regime, even if these circuits are expected to behave as switches. The existence of such solutions can also be exploited for control purposes: operation of the system around the quasi-stable orbit allows us to turn on and off the oscillations reliably and on demand. We illustrate these ideas with a simple protocol based on optical interference that can induce oscillations robustly both in the stochastic and deterministic regimes.Comment: 24 pages, 5 main figure