TF34 engine compression system computer study

The stability of the fan and the compressor components was examined individually using linearized and time dependent, one dimensional stability analysis techniques. The stability of the fan core integrated compression system was investigated using a two dimensional compression system model. The analytical equations on which this model was based satisfied the mass, axial momentum, radial momentum, and energy conservation equations for flow through a finite control volume. The results gave an accurate simulation of the flow through the compression system. The speed lines of the components were reproduced; the points of instability were accurately predicted; the locations where the instability was initiated in the fan and the core were indicated; and the variation of the bypass ratio during flow throttling was calculated. The validity of the analytical techniques was then established by comparing these results with test data and with results obtained from the steady state cycle deck

Minimum weight design of symmetrically stiffened orthotropic cylinders under axial compression

Minimum weight design of symmetrically stiffened orthotropic cylinders under axial compressio

Self-organizing lists on the Xnet

The first parallel designs for implementing self-organizing lists on the Xnet interconnection network are presented. Self-organizing lists permute the order of list entries after an entry is accessed according to some update hueristic. The heuristic attempts to place frequently requested entries closer to the front of the list. This paper outlines Xnet systems for self-organizing lists under the move-to-front and transpose update heuristics. Our novel designs can be used to achieve high-speed lossless text compression

Implementation of JPEG compression and motion estimation on FPGA hardware

A hardware implementation of JPEG allows for real-time compression in data intensivve applications, such as high speed scanning, medical imaging and satellite image transmission. Implementation options include dedicated DSP or media processors, FPGA boards, and ASICs. Factors that affect the choice of platform selection involve cost, speed, memory, size, power consumption, and case of reconfiguration. The proposed hardware solution is based on a Very high speed integrated circuit Hardware Description Language (VHDL) implememtation of the codec with prefered realization using an FPGA board due to speed, cost and flexibility factors; The VHDL language is commonly used to model hardware impletations from a top down perspective. The VHDL code may be simulated to correct mistakes and subsequently synthesized into hardware using a synthesis tool, such as the xilinx ise suite. The same VHDL code may be synthesized into a number of sifferent hardware architetcures based on constraints given. For example speed was the major constraint when synthesizing the pipeline of jpeg encoding and decoding, while chip area and power consumption were primary constraints when synthesizing the on-die memory because of large area. Thus, there is a trade off between area and speed in logic synthesis

Resistojet systems studies directed to the space station/space base. Volume 2 - Biowaste resistojet system development program Final report

Space station/base biowaste resistojet system for orbit keeping and control moment gyro desaturation - systems developmen