7 research outputs found
Analysis and design of switched-capacitor DC-DC converters with discrete event models
Ph. D. Thesis.Switched-capacitor DC-DC converters (SCDDCs) play a critical role in low power
integrated systems. The analysis and design processes of an SCDDC impact the
performance and power efficiency of the whole system. Conventionally, researchers carry
out the analysis and design processes by viewing SCDDCs as analogue circuits. Analogue
attributes of an SCDDC, such as the charge flow current or the equivalent output impedance,
have been studied in considerable detail for performance enhancement. However, in most
existing work, less attention is paid to the analysis of discrete events (e.g. digital signal
transitions) and the relationships between discrete events in SCDDCs. These discrete
events and the relationships between discrete events also affect the performance of
SCDDCs. Certain negative effects of SCDDCs such as leakage current are introduced by
unhealthy discrete states. For example, MOS devices in an SCDDC could conduct
undesirably under certain combinations of signals, resulting in reversion losses (a type of
leakage in SCDDCs). However, existing work only use verbal reasoning and waveform
descriptions when studying these discrete events, which may cause confusion and result in
an informal design process consisting of intuitive design and backed up merely by
validation based on natural language discussions and simulations. There is therefore a need
for formalised methods to describe and analyse these discrete events which may facilitate
systematic design techniques.
This thesis presents a new method of analysing and designing SCDDCs using discrete event
models. Discrete event models such as Petri nets and Signal Transition Graphs (STGs) are
commonly used in asynchronous circuits to formally describe and analyse the relationships
between discrete transitions. Modelling SCDDCs with discrete event models provides a
formal way to describe the relations between discrete transitions in SCDDCs. These
discrete event models can be used for analysis, verification and even design guidance for
SCDDC design. The rich set of existing analysis methods and tools for discrete event
models could be applied to SCDDCs, potentially improving the analysis and design flow
for them. Moreover, since Petri nets and STGs are generally used to analyse and design
asynchronous circuits, modelling and designing SCDDCs with STG models may
additionally facilitate the incorporation of positive features of asynchronous circuits in
SCDDCs (e.g. no clock skew). In this thesis, the relations between discrete events in SCDDCs are formally described with
SC-STG (an extended STG targeting multi-voltage systems, to which SCDDCs belong),
which avoids the potential confusion due to natural language and waveform descriptions.
Then the concurrency and causality relations described in SC-STG model are extended to
Petri nets, with which the presence of reversion losses can be formally determined and
verified. Finally, based on the STG and Petri net models, a new design method for
reversion-loss-free SCDDCs is proposed. In SCDDCs designed with the new method,
reversion losses are entirely removed by introducing asynchronous controls, synthesised
with the help of a software synthesis toolkit “Workcraft”.
To demonstrate the analysis capabilities of the method, several cross-coupled voltage
doublers (a type of SCDDC) are analysed and studied with discrete event models as
examples in this thesis. To demonstrate the design capabilities of the method, a new
reversion-loss-free cross-coupled voltage doubler is designed. The cross-coupled voltage
doubler is widely used in low power integrated systems such as flash memories, LCD
drivers and wireless energy harvesting systems. The proposed modelling method is
potentially used in both research and industrial area of those applications for a formal and
high-efficiency design proces
Exploiting robustness in asynchronous circuits to design fine-tunable systems
PhD ThesisRobustness property in a circuit defines its tolerance to the effects of process, voltage and
temperature variations. The mode signaling and event communication between computing
units in a asynchronous circuits makes them inherently robust. The level of robustness
depends on the type of delay assumptions used in the design and specification process.
In this thesis, two approaches to exploiting robustness in asynchronous circuits to design
self-adapting and fine-tunable systems are investigated. In the first investigation, a Digitally
Controllable Oscillator (DCO) and a computing unit are integrated such that the operating
conditions of the computing unit modulated the operation of the DCO. In this investigation,
the computing unit which is a self-timed counter interacts with the DCO in a four-phase
handshake protocol. This mode of interaction ensures a DCO and computing unit system
that can fine-tune its operation to adapt to the effects of variations. In this investigation, it
is shown that such a system will operate correctly in wide range of voltage supply. In the
second investigation, a Digital Pulse-Width Modulator (DPWM) with coarse and fine-tune
controls is designed using two Kessels counters. The coarse control of the DPWM tuned the
pulse ratio and pulse frequency while the fine-tune control exploited the robustness property
of asynchronous circuits in an addition-based delay system to add or subtract delay(s) to
the pulse width while maintaining a constant pulse frequency. The DPWM realized gave
constant duty ratio regardless of the operating voltage. This type of DPWM has practical
application in a DC-DC converter circuit to tune the output voltage of the converter in high
resolution. The Kessels counter is a loadable self-timed modulo−n counter, which is realized
by decomposition using Horner’s method, specified and verified using formal asynchronous
design techniques. The decomposition method used introduced parallelism in the system by
dividing the counter into a systolic array of cells, with each cell further decomposed into
two parts that have distinct defined operations. Specification of the decomposed counter cell
parts operation was in three stages. The first stage employed high-level specification using
Labelled Petri nets (LPN). In this form, functional correctness of the decomposed counter is
modelled and verified. In the second stage, a cell part is specified by combing all possible
operations for that cell part in high-level form. With this approach, a combination of inputs
from a defined control block activated the correct operation for a cell part. In the final stage,
the LPNs were converted to Signal Transition Graphs, from which the logic circuits of the
cells were synthesized using the WorkCraft Tool. In this thesis, the Kessels counter was
implemented and fabricated in 350 nm CMOS Technology.Niger Delta Development Commission (NDD