C-MOS array design techniques: SUMC multiprocessor system study

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units

Microprocessor based modular support for an operating system

A technique to support the operating system has been presented. The approach utilizes a modular microprocessor based support system to parallel process and/or assist some operating system funtional units. Adopting the proposed technique may result in reducing the amount of processing power devoted to the execution of the operating system code as well as in reducing overall system cost;Two application examples of the proposed technique have been invented. The first is a support module for Habermann\u27s deadlock avoidance algorithm. Without the support module, the algorithm would have an execution time O(m(\u272)), where m is the number of processes in the system. The design and operation of a support module that employs m + 1 microprocessors and is capable of performing the algorithm with an execution time O(m) has been described. Another module utilizes (m/k) + 1 microprocessors, and has an execution time O(km), k \u3e 1, has been discussed. This latter module is suitable when m is very large. A fast module that has an execution time O(km), k \u3c 1, and is appropriate for systems with small m has also been discussed;The second application example is a support module for the exact implementation of the Least Recently Used (LRU) replacement policy in a demand paging memory management system. It was believed that the exact implementation of the LRU was not feasible because it would represent a tremendous overhead. This is no longer true if the proposed technique is considered. A submodule that employs an MC68000 microprocessor was designed and built to execute the exact LRU function. To test the submodule, it was found necessary to build an address stream generator module to simulate the main system. Therefore, an address stream generation module was built around another MC68000 microprocessor. The LRU submodule was then extensively tested under different address arrival rates. The data obtained from the experiments prove the feasibility of implementing the exact LRU algorithm at a very low cost. It also largely endorses the proposed support technique

A model of a multiprogrammed demand paging computer system.

Massachusetts Institute of Technology. Dept. of Electrical Engineering. Thesis. 1973. M.S.MICROFICHE COPY ALSO AVAILABLE IN BARKER ENGINEERING LIBRARY.Includes bibliographical references.M.S

Information systems to provide leading indicators of energy sufficiency : a report to the Federal Energy Administration

Final working paper, submitted to Office of Data Policy, Federal Energy Administration in connection with A Study of information systems to provide leading indicators of energy sufficiency, (FEA Contract no. 14-01-001-2040)

NBS monograph

From Introduction: "This is the second in a series of reports concerned with research and development requirements and areas of continuing concern in the computer and information sciences and technologies.