3 research outputs found
Polarity Control at Runtime:from Circuit Concept to Device Fabrication
Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to overcome physical limitations affecting conventional CMOS technology. Here, we propose a novel Schottky barrier device concept based on electrostatic polarity control. Specifically, this device can behave as p- or n-type by simply changing an electric input bias. This device combines More-than-Moore and Beyond CMOS elements to create an efficient technology with a viable path to Very Large Scale Integration (VLSI). This thesis proposes a device/circuit/architecture co-optimization methodology, where aspects of device technology to logic circuit and system design are considered. At device level, a full CMOS compatible fabrication process is presented. In particular, devices are demonstrated using vertically stacked, top-down fabricated silicon nanowires with gate-all-around electrode geometry. Source and drain contacts are implemented using nickel silicide to provide quasi-symmetric conduction of either electrons or holes, depending on the mode of operation. Electrical measurements confirm excellent performance, showing Ion/Ioff > 10^7 and subthreshold slopes approaching the thermal limit, SS ~ 60mV/dec (~ 63mV/dec) for n(p)-type operation in the same physical device. Moreover, the shown devices behave as p-type for a polarization bias (polarity gate voltage, Vpg) of 0V, and n-type for a Vpg = 1V, confirming their compatibility with multi-level static logic circuit design. At logic gate level, two- and four-transistor logic gates are fabricated and tested. In particular, the first fully functional, two-transistor XOR logic gate is demonstrated through electrical characterization, confirming that polarity control can enable more compact logic gate design with respect to conventional CMOS. Furthermore, we show for the first time fabricated four- transistors logic gates that can be reconfigured as NAND or XOR only depending on their external connectivity. In this case, logic gates with full swing output range are experimentally demonstrated. Finally, single device and mixed-mode TCAD simulation results show that lower Vth and more optimized polarization ranges can be expected in scaled devices implementing strain or high-k technologies. At circuit and system level, a full semi-custom logic circuit design tool flow was defined and configured. Using this flow, novel logic libraries based on standard cells or regular gate fabrics were compared with standard CMOS. In this respect, results were shown in comparison to CMOS, including a 40% normalized area-delay product reduction for the analyzed standard cell libraries, and improvements of over 2× in terms of normalized delay for regular Controlled Polarity (CP)-based cells in the context of Structured ASICs. These results, in turn, confirm the interest in further developing and optimizing CP devices, as promising candidates for future digital circuit technology
Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits
Title from PDF of title page viewed August 28, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 120-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016Floating gate transistor is the basic building block of non-volatile flash memory, which
is one of the most widely used memory gadgets in modern micro and nano electronic
applications. Recently there has been a surge of interest to introduce a new generation of
memory devices using graphene nanotechnology. In this paper we present a new floating gate
transistor (FGT) design based on multilayer graphene nanoribbon (MLGNR) and carbon
nanotube (CNT). In the proposed graphene based floating gate transistor (GFGT) a multilayer
structure of graphene nanoribbon (GNR) would be used as the channel of the field effect
transistor (FET) and a layer of CNTs would be used as the floating gate. We have performed
an analysis of the charge accumulation mechanism in the floating gate and its dependence on
the applied terminal voltages. Based on our analysis we have observed that proposed graphene
based floating gate transistor could be operated at a reduced voltage compared to conventional
silicon based floating gate devices. We have presented detail analysis of the operation and the
programming and erasing processes of the proposed FGT, dependency of the programming
and erasing current density on different parameters, impact of scaling the thicknesses of the
control and tunneling oxides. These analyses are done based on the equivalent capacitance
model of the device.
We have analyze the programming and erasing by the tunneling current mechanism in
the proposed graphene-CNT floating gate transistor. In this paper, we have investigated the
mechanism of programming current and the factors that would influence this current and the
behavior of the proposed floating gate transistor. The analysis reveals that programming is a
strong function of the high field induced by the control gate, and the thicknesses of the control
oxide and the tunnel oxide.
With the growing demand for nonvolatile flash memory devices and increasing
limitations of silicon technologies, there has been a growing interest to develop emerging flash
memory by using alternative nanotechnology. The proposed FGT device for nonvolatile flash
memory contains an MLGNR channel and a CNT floating gate with SiO₂ as the tunnel oxide.
In this paper, we have presented detail analysis of the electrical properties and performance
characteristics of the proposed FGT device. We have focused on the following aspects: current
voltage (I-V) characteristics, threshold voltage variation (∆VTH), programming, erasing and
reading power consumptions compared to the existing FGTs, and layer-by-layer current
voltage characteristics comparison of the proposed GFGT device. To realize graphene field
effect transistor (GFET), a general model is developed, validated and analyzed. This model is
also used to estimate graphene channel behavior of the proposed GFGT.
Reliability is the major concern of the Flash memory technology. We have analyzed
retention characteristics of the proposed GFGT. We also have developed a radiation harness
test model for the Si-FGT by using VTH variation principle due to the radiation exposure. Flash
memory experiences adverse effects due to radiation. These effects can be raised in terms of
doping, feature size, supply voltages, layout, shielding. The operating point shift of the device
forced to enter the logically-undefined region and cause upset and data errors under radiation
exposure. In this research, the threshold voltage shift of the floating gate transistor (FGT) is
analyzed by a mathematical model.
Molybdenum disulfide (MoS2) based field effect transistor is considered as one of the
promising future logic devices. Many other nanoelectronic devices based on MoS2 are
currently under investigation. However, the challenge of providing reliable and efficient
contact between 2D materials like MoS2 and the metal is still unresolved. The contact
resistance between metal and MoS2 limits the application of MoS2 in current semiconductor
technologies. In this paper, a detail analysis of metal-MoS2 contact has been presented.
Specific contributions of this work are:investigation of the physical, material and electrical
parameters that would determine the contact properties, analysis of the combined impact of the
top and back gates for the first time, modeling of the crucial metal-MoS2 contact parameters,
such as, sheet resistance (RSh), contact resistivity (ρc), contact resistance (RC) and transfer
length (LT), investigation of the ways to incorporate the developed contact model into the
electronic design automation (EDA) tools and investigation of different contact materials for
the metal-MoS2 contact.
The three dimensional integrated circuit (3D- IC) is expected to extend Moore's law.
To reduce interconnects and time delay, semiconductor industry is shifting 2D-IC to 2.5D-IC
and 3D-IC. 3D-IC is the ultimate goal of the semiconductor industry, where 2.5D-IC is an
intermediate state. It is important to realize CAD design challenges of the 2.5D-IC/3D-IC when
minimum spacing interconnects are used. The major contributions of this research work are as
follows. Previously, for the small scale experimental purpose, small numbers (10-20) of TSVs,
interconnects, bumps are fabricated together by hand calculation. However in the real 3D-IC
design, thousands of TSVs, interconnects, bumps are reuired. Therefore, an automated CAD
solution is required to provide precise physical design and verification. Therefore, a solid CAD
solution is provided here. Compatible with 40nm-technology design, which enables the Silicon
Interposer to integrate with the digital, analog and RF dies together. Dimensions and spacing
of the TSV and Bump are optimized by the 3D EM full wave field solver. To our best
knowledge, at the interposer level, this design reports the most dense and well-defined RDL,
TSV and micro-bump co-design on Silicon Interposer, which will be used for 2.5D-IC.Introduction and background -- Proposed Graphene Based Flash Memory -- Physical and Electrical Parameters of the Proposed Graphene Flash Memory Device -- Programming and Erasing Operation of the Proposed Graphene Flash Memory Device -- Reliability Analysis of the Proposed Graphene Flash Memory Device -- Radiation Hardness Analysis of the Floating Gate Transistor -- Benchmarking of the Proposed Graphene Flash Memory Device -- Graphene Field Effect Transistor (GFET) Generalized Model -- MoS2 FET Device and Contact Characterization and Modelling based on Modified Transfer Length Method (TLM) -- 2.5D Silicon Interposer Design in 40nm-Technology for 2D-IC and 3D-IC -- Conclusion and Future Wor