FIRST-ORDER MEMRISTOR-CAPACITOR FILTER CIRCUITS EMPLOYING HP MEMRISTOR

The memristor has drawn the worldwide attention since it has been discovered at HP laboratory on 1 May 2008. Since then many researchers are taking efforts to find its applications in various areas. In this paper, we study the filter characteristics of first-order low pass and high pass filters employing memristor with a capacitor. The paper provides a comparative analysis between low pass and high pass filter circuits that utilizing ordinary resistor or memristor with a capacitor. The theoretical analyzes are verified with SPICE simulation results using a memristor SPICE model with nonlinear dopant drift and MATLAB environment. The effect of change of the input frequency and initial resistance value of memristor on the cut-off frequencies of the presented low pass and high pass filters are investigated. The memory effect of memristor is represented by simulation results

Bifurcation and Chaos in Fractional-Order Systems

This book presents a collection of seven technical papers on fractional-order complex systems, especially chaotic systems with hidden attractors and symmetries, in the research front of the field, which will be beneficial for scientific researchers, graduate students, and technical professionals to study and apply. It is also suitable for teaching lectures and for seminars to use as a reference on related topics

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor