Probabilistic scenario analysis of integrated road-power infrastructures with hybrid fleets of EVs and ICVs

Electric Vehicles (EVs) are key contributors to the reduction of CO2 emissions. However, reliance on EVs must come with the guarantee that the integrated road-power infrastructure is capable of providing adequate mobility serviceability, even in case of disruption due to accidents or disturbances due to traffic jams. In this paper, we propose a probabilistic scenario analysis framework to quantify service losses in terms of delays that vehicles (both EVs and Internal Combustion Vehicles (ICVs)) may incur due to different car accident scenarios. The framework is based on modelling the System of Systems (SoS) comprised by road network, electric power system and vehicles, with graph theory and Finite State Machines (FSMs), respectively, and then embedding the model within a probabilistic scenario analysis, wherein meaningful disruption scenarios are sampled, service losses are measured (specifically as the ratio between the increase in travel time spent along the origin-destination routes on the road network following a disruption, and the corresponding travel time in nominal traffic conditions), and the economic losses and transport reliability of the infrastructure are assessed. To exemplify the application of the framework, we consider a benchmark road-power infrastructure in New York state travelled by a mixed fleet of EVs and ICVs, with different EVs penetration levels and under car accidental scenarios of different magnitudes. By using the insightful graphical representation of the results in terms of traffic volume across different road sections, the framework allows comparing alternative road-power infrastructure designs (e.g., critical roads, optimal gas and charging station locations, power network structure and topology, ...) with respect to travel times, economic service losses and transport reliability considering different nominal and disruption scenarios under different EVs penetration levels service

Low Power Design Techniques for Digital Logic Circuits.

With the rapid increase in the density and the size of chips and systems, area and power dissipationbecome critical concern in Very Large Scale Integrated (VLSI) circuit design. Low powerdesign techniques are essential for today's VLSI industry. The history of symbolic logic and sometypical techniques for finite state machine (FSM) logic synthesis are reviewed.The state assignment is used to optimize area and power dissipation for FSMs. Two costfunctions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to searchfor a good state assignment to minimize the cost functions. The algorithm has been implementedin C. The program can produce better results than NOVA, which is integrated into SIS by DCBerkeley, and other publications both in area and power tested by MCNC benchmarks.Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flopscan save power for digital systems significantly. Three new kinds of flip-flops, called differentialCMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valuedflip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice.Most researchers have focused on developing low-power techniques in AND/OR or NAND& NOR based circuits. The low power techniques for AND /XOR based circuits are still intheir early stage of development. To implement a complex function involving many inputs,a form of decomposition into smaller subfunctions is required such that the subfunctions fitinto the primitive elements to be used in the implementation. Best polarity based XOR gatedecomposition technique has been developed, which targets low power using Huffman algorithm.Compared to the published results, the proposed method shows considerable improvement inpower dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller(FPRM) forms. Based on polarity transformation, an algorithm is developed and implementedin C language which can find the best polarity for power and area optimization. Benchmarkexamples of up to 21 inputs run on a personal computer are given

Aportes a la reducción de consumo en FPGAs

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid. Escuela Politécnica Superior, Departamento de Ingeniería Informática. Fecha de lectura: 15-04-200

Finite State Machine Decomposition for Low Power

Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe a new clock-gating technique based on finite state machine (FSM) decomposition. We compute two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. This way we will have a small amount of logic that is active most of the time, during which is disabling a much larger circuit, the other sub-FSM. We provide a set of experimental results that show that power consumption can be substantially reduced, in some cases up to 80%. I