Augmented Symbolic Execution for Information Flow in Hardware Designs

We present SEIF, a methodology that combines static analysis with symbolic execution to verify and explicate information flow paths in a hardware design. SEIF begins with a statically built model of the information flow through a design and uses guided symbolic execution to recognize and eliminate non-flows with high precision or to find corresponding paths through the design state for true flows. We evaluate SEIF on two open-source CPUs, an AES core, and the AKER access control module. SEIF can exhaustively explore 10-12 clock cycles deep in 4-6 seconds on average, and can automatically account for 86-90% of the paths in the statically built model. Additionally, SEIF can be used to find multiple violating paths for security properties, providing a new angle for security verification

물리적 설계 자동화에서 표준셀 합성 및 최적화와 설계 품질 예측 방법론

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 김태환.In the physical design of chip implementation, designing high-quality standard cell layout and accurately predicting post-route DRV (design rule violation) at an early stage is an important problem, especially in advanced technology nodes. This dissertation presents two methodologies that can contribute to improving the design quality and design turnaround time of physical design flow. Firstly, we propose an integrated approach to the two problems of transistor folding and placement in standard cell layout synthesis. Precisely, we propose a globally optimal algorithm of search tree based design space exploration, devising a set of effective speeding up techniques as well as dynamic programming based fast cost computation. In addition, our algorithm incorporates the minimum oxide diffusion jog constraint, which closely relies on both of transistor folding and placement. Through experiments with the transistor netlists and design rules in advanced node, our proposed method is able to synthesize fully routable cell layouts of minimal size within a very fast time for each netlist, outperforming the cell layout quality in the manual design. Secondly, we propose a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of pin accessibility and routing congestion on DRC hotspots. Precisely, we devise a graph, called pin proximity graph, that effectively models the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML model, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using advanced node, our model outperforms the existing ML models on all benchmark designs within the fast inference time in comparison with that of the state-of-the-art techniques.칩 구현의 물리적 설계 단계에서, 높은 성능의 표준 셀 설계와 배선 연결 이후 조기에 설계 규칙 위반을 정확히 예측하는 것은 최신 공정에서 특히 중요한 문제이다. 본 논문에서는 물리적 설계에서의 설계 품질과 총 설계 시간 향상을 달성할 수 있는 두 가지 방법론을 제안한다. 먼저, 본 논문에서는 표준 셀 레이아웃 합성에서 트랜지스터 폴딩과 배치를 종합적으로 진행할 수 있는 방법론을 논한다. 구체적으로 탐색 트리 기반의 최적화 알고리즘과 동적 프로그래밍 기반 빠른 비용 계산 방법과 여러 속도 개선 기법을 제안한다. 여기에 더해, 최신 공정에서 트랜지스터 폴딩과 배치로 인해 발생할 수 있는 최소 산화물 확산 영역 설계 규칙을 고려하였다. 최신 공정에 대한 표준 셀 합성 실험 결과, 본 논문에서 제안한 방법이 설계 전문가가 수동으로 설계한 것 대비 높은 성능을 보이고, 설계 시간도 매우 짧음을 보인다. 두번째로, 본 논문에서는 셀 배치 단계에서 핀 접근성과 연결 혼잡으로 인한 영향을 종합적으로 고려할 수 있는 머신 러닝 기반 설계 규칙 위반 구역 예측 방법론을 제안한다. 먼저 표준 셀의 입/출력 핀의 물리적 정보와 핀과 핀 사이 방해 관계를 효과적으로 표현할 수 있는 핀 근접 그래프를 제안하고, 그래프 신경망과 유넷 신경망을 효과적으로 결합한 새로운 형태의 머신 러닝 모델을 제안한다. 이 모델에서 그래프 신경망은 핀 근접 그래프로부터 핀 접근성 정보를 추출하고, 유넷 신경망은 격자 기반 특징으로부터 연결 혼잡 정보를 추출한다. 실험 결과 본 논문에서 제안한 방법은 이전 연구들 대비 더 빠른 예측 시간에 더 높은 예측 성능을 달성함을 보인다.1 Introduction 1 1.1 Standard Cell Layout Synthesis 1 1.2 Machine Learning for Electronic Design Automation 6 1.3 Prediction of Design Rule Violation 8 1.4 Contributions of This Dissertation 11 2 Standard Cell Layout Synthesis of Advanced Nodes with Simultaneous Transistor Folding and Placement 14 2.1 Motivations 14 2.2 Algorithm for Standard Cell Layout Synthesis 16 2.2.1 Problem Definition 16 2.2.2 Overall Flow 18 2.2.3 Step 1: Generation of Folding Shapes 18 2.2.4 Step 2: Search-tree Based Design Space Exploration 20 2.2.5 Speeding up Techniques 23 2.2.6 In-cell Routability Estimation 28 2.2.7 Step 3: In-cell Routing 30 2.2.8 Step 4: Splitting Folding Shapes 35 2.2.9 Step 5: Relaxing Minimum-area Constraints 37 2.3 Experimental Results 38 2.3.1 Comparison with ASAP 7nm Cell Layouts 40 2.3.2 Effectiveness of Dynamic Folding 42 2.3.3 Effectiveness of Speeding Up Techniques 43 2.3.4 Impact of Splitting Folding Shape 48 2.3.5 Runtime Analysis According to Area Relaxation 51 2.3.6 Comparison with Previous Works 52 3 Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction using Graph Neural Network and U-Net 54 3.1 Preliminary 54 3.1.1 Graph Neural Network 54 3.1.2 Fully Convolutional Network 56 3.2 Proposed Prediction Methodology 57 3.2.1 Overall Flow 57 3.2.2 Pin Proximity Graph 58 3.2.3 Grid-based Features 61 3.2.4 Overall Architecture of PGNN 64 3.2.5 GNN Architecture in PGNN 64 3.2.6 U-net Architecture in PGNN 66 3.2.7 Final Prediction in PGNN 66 3.3 Experimental Results 68 3.3.1 Experimental Setup 68 3.3.2 Analysis on PGNN Performance 71 3.3.3 Comparison with Previous Works 72 3.3.4 Adaptation to Real-world Designs 81 3.3.5 Handling Data Imbalance Problem in Regression Model 86 4 Conclusions 92 4.1 Chapter 2 92 4.2 Chapter 3 93박

Tools and Algorithms for the Construction and Analysis of Systems

This open access two-volume set constitutes the proceedings of the 27th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2021, which was held during March 27 – April 1, 2021, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2021. The conference was planned to take place in Luxembourg and changed to an online format due to the COVID-19 pandemic. The total of 41 full papers presented in the proceedings was carefully reviewed and selected from 141 submissions. The volume also contains 7 tool papers; 6 Tool Demo papers, 9 SV-Comp Competition Papers. The papers are organized in topical sections as follows: Part I: Game Theory; SMT Verification; Probabilities; Timed Systems; Neural Networks; Analysis of Network Communication. Part II: Verification Techniques (not SMT); Case Studies; Proof Generation/Validation; Tool Papers; Tool Demo Papers; SV-Comp Tool Competition Papers

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Towards Optimal Application Mapping for Energy-Efficient Many-Core Platforms

Siirretty Doriast

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Combining dynamic and static scheduling in high-level synthesis

Field Programmable Gate Arrays (FPGAs) are starting to become mainstream devices for custom computing, particularly deployed in data centres. However, using these FPGA devices requires familiarity with digital design at a low abstraction level. In order to enable software engineers without a hardware background to design custom hardware, high-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low-level hardware description. A central task in HLS is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile time, but recent years have seen the emergence of dynamic scheduling, in which an operation’s clock cycle is only determined at run-time. Both approaches have their merits: static scheduling can lead to simpler circuitry and more resource sharing, while dynamic scheduling can lead to faster hardware when the computation has a non-trivial control flow. This thesis proposes a scheduling approach that combines the best of both worlds. My idea is to use existing program analysis techniques in software designs, such as probabilistic analysis and formal verification, to optimize the HLS hardware. First, this thesis proposes a tool named DASS that uses a heuristic-based approach to identify the code regions in the input program that are amenable to static scheduling and synthesises them into statically scheduled components, also known as static islands, leaving the top-level hardware dynamically scheduled. Second, this thesis addresses a problem of this approach: that the analysis of static islands and their dynamically scheduled surroundings are separate, where one treats the other as black boxes. We apply static analysis including dependence analysis between static islands and their dynamically scheduled surroundings to optimize the offsets of static islands for high performance. We also apply probabilistic analysis to estimate the performance of the dynamically scheduled part and use this information to optimize the static islands for high area efficiency. Finally, this thesis addresses the problem of conservatism in using sequential control flow designs which can limit the throughput of the hardware. We show this challenge can be solved by formally proving that certain control flows can be safely parallelised for high performance. This thesis demonstrates how to use automated formal verification to find out-of-order loop pipelining solutions and multi-threading solutions from a sequential program.Open Acces

Emerging research directions in computer science : contributions from the young informatics faculty in Karlsruhe

In order to build better human-friendly human-computer interfaces, such interfaces need to be enabled with capabilities to perceive the user, his location, identity, activities and in particular his interaction with others and the machine. Only with these perception capabilities can smart systems ( for example human-friendly robots or smart environments) become posssible. In my research I\u27m thus focusing on the development of novel techniques for the visual perception of humans and their activities, in order to facilitate perceptive multimodal interfaces, humanoid robots and smart environments. My work includes research on person tracking, person identication, recognition of pointing gestures, estimation of head orientation and focus of attention, as well as audio-visual scene and activity analysis. Application areas are humanfriendly humanoid robots, smart environments, content-based image and video analysis, as well as safety- and security-related applications. This article gives a brief overview of my ongoing research activities in these areas