Mikrovian elektrolyyttisen täyttöpinnoitus: malli prosessimonitoroinnin kehitystä varten

Mikrovia on monikerrospiirilevyn yhden levyn läpi kulkeva reikä. Täyttämällä tämä reikä kuparilla muodostetaan yhteys kahdessa eri piirilevykerroksessa kulkevien johdinpiirien välille. Mikroviateknologia yhdistettynä moderniin piirisuunnitteluun mahdollistaa piirilevyjen johdintiheyden kasvattamisen ja näin ollen piirilevyjen sekä niille rakentuvien laitteiden pienentämisen. Viareiät täytetään elektrolyyttisesti rikkihappo-kuparisulfaatti-liuoksesta. Täyttöpinnoitusprosessissa mikrovia täyttyy täydellisesti kuparimetallilla ja reiän kohdalle jää peilikirkas kuparipinta valmiiksi seuraavan piirilevykerroksen ladontaa varten. Prosessin onnistuminen edellyttää kuparin pinnoittumista elektrolyyttiliuoksesta piirilevylle hallitun epätasaisesti siten, että kuparia pelkistyy eniten sinne, missä pinnassa on syvin reikä ja vähemmän sinne, missä pinta on tasainen tai siinä on kohouma. Ilmiö saadaan aikaan erityisten pinnoituslisäaineiden avulla. Mikroviojen pinnoitusastetta ei voida pinnoituksen aikana mitenkään mitata ja prosessin lunnonilmiöt huomioon ottava malli on ainut rationaalinen tapa arvioida pinnoituksen etenemistä. Tässä diplomityössä on kehitetty täyttöpinnoitusprosessin malli, joka luo perustan prosessin mallipohjaiselle ohjaukselle. Työssä esitellään pinnoitusprosessiin liittyvät perusilmiöt: diffuusion ja migraation aiheuttama massansiirto, sähkökemiallisen reaktion jännite-virta-tasapaino sekä läpivientireiän muodon muuttumisen vaikutukset. Kirjallisuusosassa käydään läpi monipuolisesti eri pinnoituslisäaineet sekä prosessissa esiintyvät pintakemialliset ilmiöt. Työssä kehitetty malli on toteutettu elementtimenetelmää käyttäen. Malli ottaa huomioon kaikki pinnoitusprosessin oleelliset fysikaaliset ja kemialliset ilmiöt sekä mallituskohteen muodonmuutokset. Myös pinnoituslisäaineiden vaikutus sisältyy malliin. Malli ennustaa pinnoitusprosessin vaatiman pinnoitusajan annetuissa prosessiolosuhteissa kohtalaisesti. Täyttöpinnoitusprosessin monimutkaisuuden sekä prosessiin liittyvien liikesalaisuuksien takia työn tulosta voidaan pitää hyödyllisenä. Kehitetty malli on sinällään käyttövalmis ja työn myötä täyttöpinnoitusprosessien ongelmakenttä on kartoitettu ja sen systemaattinen ratkaisu voi jatkua. Työn lopuksi kerrotaan tärkeimmät jatkotutkimuksen kohteet sekä niihin liittyvät koe- ja tutkimussuunnitelmat

Modelling and control of variability in PCB copper electroplating

This thesis is concerned with the modelling and control of the acid copper electroplating process for the manufacturing of printed circuit boards (PCB). The objectives of this study were to investigate the effects of process and product parameters on the workpiece level uniformity during the acid copper plating of lithographic patterns, plated-through holes (PTH) and blind-via (BV), and to explore the minimization of the deposit thickness variation. The parameters studied were the average current density (ACD), plating duration, concentration of additive and sulphuric acid, electrode separation (ES), line width and active area density ratio (AADR) of the circuit pattern. The effects of the copper sulphate concentration, aspect ratio (CAR) and depth ratio were also studied for the PTH and BV plating. The results of the study enhance the understanding of the limitations of applying current distribution and statistical models to the copper electroplating of PCB at a workpiece level. Multifactor two-level factorial and the central composite rotatable five-level experiments were designed, and a total of fourteen sets of experiment were conducted sequentially and used to generate statistical process models. For the plating of uniform patterns, ACD, ES and their quadratic effects were found to be significant and a 6- term second order model was built and verified to predict and minimize the workpiece level variability. The existence of a minimum plating variability was attributed to the minimum deviation from the Faraday's nominal thickness observed under a particular combination of ACD and ES. For non-uniform patterns, ACD, AADR and the ACD x ES interaction were found significant and an 8-term first-order prediction model was constructed. The minimum variability achievable was found to increase with the AADR, and was explained by the scattering effect of AADR on the average plating thickness. Verification of the model with patterns of same AADR but different line width revealed the limitation of the continuum concept, i. e. AADR alone is not sufficient to characterize a non-uniformly patterned substrate. Subsequent verification runs using a simple circuit pattern showed further that a composite parameter involving the overall active area density, the continuum area and the number of AAD contrasts, was appropriate. For the PTH plating, ACD, CAR, ACD2 and the ACD x ES, ES x CAR interactions were found significant but only ES, ES2 and ACD x ES were active for BV plating. Second-order models were also developed for the two processes in their respective optimum regions and verified experimentally. The optimum values of ACD and ES, and the minimum variability achievable were found to increase with the corrected aspect ratio of the through-hole. Given the difference in the optimum regions of the PTH and BV plating, a new response surface of the PTH process was constructed at the optimum region of the BV process and vice versa. The process limiting the workpiece level uniformity under different combinations of ACD and ES was found by the intersections of these responses surfaces. Finally, process parameters limiting the simultaneous minimization of the plating variability of pattern, PTH and BV were discussed. It showed that under most situations, the workpiece level variability of BVs was higher than that of the PTHs

Electrodeposition of indium bumps for ultrafine pitch interconnections

Microelectronics integration continuously follows the trend of miniaturisation for which the technologies enabling fine pitch interconnection are in high demand. The recent advancement in the assembly of Hybrid Pixel Detectors, a high resolution detecting and imaging device, is an example of where novel materials and processes can be applied for ultra-fine pitch interconnections. For this application, indium is often used for the fine pitch bump bonding process due to its unique properties that make it especially suitable, in particular in a cryogenic environment where some types of detector have to serve. Indium bumps are typically fabricated through vacuum evaporation at the wafer level; however, this thesis investigates an alternative low cost manufacturing process at the wafer scale for the deposition of indium micro-bumps through electroplating. The work has placed its emphasis on the requirements of future technologies which will enable a low temperature ( 40,000 IOs/cm2) with a high throughput and high production yield. This research is a systematic investigation of the wafer-scale indium bumping process through electrodeposition using indium sulphamate solution. An intensive experimental study of micro-bump formation has been carried out to elaborate the effects of two of the main electroplating factors that can significantly influence the quality of bumps in the course of electrodeposition, namely the current distribution and mass transport. To adjust the current density distribution, various waveforms of current input, including direct current (DC), unipolar pulse current and bipolar pulse reverse current, were employed in the experiments. To assist mass transportation prior to or during electroplating, acoustic agitation including ultrasonic agitation at 30 kHz frequency as well as megasonic agitation at 1 MHz, were utilised. The electrochemical properties of the indium sulphamate solution were first investigated using non-patterned plain substrates prior to indium bumping trials. This provided understanding of the microstructural characteristics of indium deposits produced by electroplating and, through cathodic polarisation measurements, the highest current density suitable for electrodeposition was achieved as approximately 30 mA/cm2 when electroplating was carried out at room temperature and with no agitation applied. The typical surface morphology of DC electroplated indium contained a granular structure with a surface feature size as large as 10 µm. Pulse and pulse reverse electroplating significantly altered the surface morphology of the deposits and the surface became much smoother. By introducing acoustic agitation, the current density range suitable for electrodeposition could be significantly expanded due to the greater mass transfer, which led to a higher speed of deposition with high current efficiency. Wafer-scale indium bumping (15 µm to 25 µm diameter) at a minimum pitch size of 25 µm was successfully developed through electroplating trials with 3 inch test wafers and subsequently applied onto the standard 4 inch wafers. The results demonstrate the capability of electroplating to generate high quality indium bumps with ultrafine pitch at a high consistency and yield. To maximise the yield, pre-wetting of the ultrafine pitch photoresist patterns by both ultrasonic or megasonic agitation is essential leading to a bumping yield up to 99.9% on the wafer scale. The bump profiles and their uniformity at both the wafer and pattern scale were measured and the effects of electrodeposition regimes on the bump formation evaluated. The bump uniformity and microstructure at the feature scale were also investigated by cross-sectioning the electroplated bumps from different locations on the wafers. The growth mechanism of indium bumps were proposed on the basis of experimental observation. It was found that the use of a conductive current thief ring can homogenise the directional bump uniformity when the electrical contact is made asymmetrically, and improve the overall uniformity when the electrical contact is made symmetrically around the periphery of the wafer. Both unipolar pulse electroplating and bipolar pulse reverse electroplating improved the uniformity of the bump height at the wafer scale and pattern scale, and the feature scale uniformity could be significantly improved by pulse reverse electroplating. The best uniformity of 13.6% for a 4 inch wafer was achieved by using pulse reverse electroplating. The effect of ultrasonic agitation on the process was examined, but found to cause damage to the photoresist patterns if used for extended periods and therefore not suitable for use throughout indium bumping. Megasonic agitation enabled high speed bumping without sacrifice of current efficiency and with little damage to the photoresist patterns. However, megasonic agitation tended to degrade some aspects of wafer scale uniformity and should therefore be properly coupled with other electroplating parameters to assist the electroplating process.EThOS - Electronic Theses Online ServiceGBUnited Kingdo