Design of energy efficient high speed I/O interfaces

Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input

Airborne range and orbit determination design study- volumes i - iv final report

Airborne Range and Orbit Determination systems design, development, assembly, testing, and analysi

Systems design study of the Pioneer Venus spacecraft. Appendices to volume 1, sections 8-11 (part 3 of 3)

Power subsystem cost/weight tradeoffs are discussed for the Venus probe spacecraft. The cost estimations of power subsystem units were based upon DSCS-2, DSP, and Pioneer 10 and 11 hardware design and development and manufacturing experience. Parts count and degree of modification of existing hardware were factored into the estimate of manufacturing and design and development costs. Cost data includes sufficient quantities of units to equip probe bus and orbiter versions. It was based on the orbiter complement of equipment, but the savings in fewer slices for the probe bus balance the cost of the different probe bus battery. The preferred systems for the Thor/Delta and for the Atlas/Centaur are discussed. The weights of the candidate designs were based upon slice or tray weights for functionally equivalent circuitry measured on existing hardware such as Pioneers 10 and 11, Intelsat 3, DSCS-2, or DSP programs. Battery weights were based on measured cell weight data adjusted for case weight or off-the-shelf battery weights. The solar array weight estimate was based upon recent hardware experience on DSCS-2 and DSP arrays

TDRSS multimode transponder program. Phase 2: Equipment development

This report contains a complete description of the TDRS Multimode Transponder and its associated ground support equipment. The transponder will demonstrate candidate modulation techniques to provide the required information for the design of an eventual VHF/UHF transponder suitable for installation in a user satellite, capable of operating as part of a Tracking and Data Relay Satellite (TDRS) systems. Use of geosynchronous TDRS which can serve both low data rate users at VHF and high data rate users at other frequencies has been considered. The effects of radio frequency interference from the earth and of multipath propagation due to reflections from the earth are expected to pose problems for the TDRS system at VHF. Investigations have suggested several modulation techniques that offer promise to overcome these problems

Cumulative index to NASA Tech Briefs, 1970-1975

Tech briefs of technology derived from the research and development activities of the National Aeronautics and Space Administration are presented. Abstracts and indexes of subject, personal author, originating center, and tech brief number for the 1970-1975 tech briefs are presented

The 25th Annual Precise Time and Time Interval (PTTI) Applications and Planning Meeting

Papers in the following categories are presented: recent developments in rubidium, cesium, and hydrogen-based frequency standards, and in cryogenic and trapped-ion technology; international and transnational applications of precise time and time interval (PTTI) technology with emphasis on satellite laser tracking networks, GLONASS timing, intercomparison of national time scales and international telecommunication; applications of PTTI technology to the telecommunications, power distribution, platform positioning, and geophysical survey industries; application of PTTI technology to evolving military communications and navigation systems; and dissemination of precise time and frequency by means of GPS, GLONASS, MILSTAR, LORAN, and synchronous communications satellites

Graduate Catalog, 1999-2002, New Jersey Institute of Technology

https://digitalcommons.njit.edu/coursecatalogs/1004/thumbnail.jp

Graduate Catalog, 1996-1999, New Jersey Institute of Technology

https://digitalcommons.njit.edu/coursecatalogs/1003/thumbnail.jp