Fixed-outline bus-driven floorplanning.

Jiang, Yan.Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.Includes bibliographical references (p. 87-92).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Physical Design --- p.2Chapter 1.2 --- Floorplanning --- p.6Chapter 1.2.1 --- Floorplanning Objectives --- p.7Chapter 1.2.2 --- Common Approaches --- p.8Chapter 1.3 --- Motivations and Contributions --- p.14Chapter 1.4 --- Organization of the Thesis --- p.15Chapter 2 --- Literature Review on BDF --- p.17Chapter 2.1 --- Zero-Bend BDF --- p.17Chapter 2.1.1 --- BDF Using the Sequence-Pair Representation --- p.17Chapter 2.1.2 --- Using B*-Tree and Fast SA --- p.20Chapter 2.2 --- Two-Bend BDF --- p.22Chapter 2.3 --- TCG-Based Multi-Bend BDF --- p.25Chapter 2.3.1 --- Placement Constraints for Bus --- p.26Chapter 2.3.2 --- Bus Ordering --- p.28Chapter 2.4 --- Bus-Pin-Aware BDF --- p.30Chapter 2.5 --- Summary --- p.33Chapter 3 --- Fixed-Outline BDF --- p.35Chapter 3.1 --- Introduction --- p.35Chapter 3.2 --- Problem Formulation --- p.36Chapter 3.3 --- The Overview of Our Approach --- p.36Chapter 3.4 --- Partitioning --- p.37Chapter 3.4.1. --- The Overview of Partitioning --- p.38Chapter 3.4.2 --- Building a Hypergraph G --- p.39Chapter 3.5 --- Floorplaiining with Bus Routing --- p.43Chapter 3.5.1 --- Find Bus Routes --- p.43Chapter 3.5.2 --- Realization of Bus Routes --- p.48Chapter 3.5.3 --- Details of the Annealing Process --- p.50Chapter 3.6 --- Handle Fixed-Outline Constraints --- p.52Chapter 3.7 --- Bus Layout --- p.52Chapter 3.8 --- Experimental Results --- p.56Chapter 3.9 --- Summary --- p.61Chapter 4 --- Fixed-Outline BDF with L-shape bus --- p.63Chapter 4.1 --- Introduction --- p.63Chapter 4.2 --- Problem Formulation --- p.64Chapter 4.3 --- Our Approach --- p.65Chapter 4.3.1 --- Bus Routability Checking --- p.67Chapter 4.3.2 --- Details of the Annealing Process --- p.79Chapter 4.4 --- Experimental Results --- p.79Chapter 4.5 --- Summary --- p.82Chapter 5 --- Conclusion --- p.85Bibliography --- p.9

Bus-driven floorplanning.

Law Hoi Ying.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 101-106).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- VLSI Design Cycle --- p.2Chapter 1.2 --- Physical Design Cycle --- p.6Chapter 1.3 --- Floorplanning --- p.10Chapter 1.3.1 --- Floorplanning Objectives --- p.11Chapter 1.3.2 --- Common Approaches --- p.12Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14Chapter 1.4 --- Motivations and Contributions --- p.15Chapter 1.5 --- Organization of the Thesis --- p.17Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18Chapter 2.1 --- Types of Floorplans --- p.18Chapter 2.2 --- Floorplan Representations --- p.20Chapter 2.2.1 --- Slicing Floorplan --- p.21Chapter 2.2.2 --- Non-slicing Floorplan --- p.22Chapter 2.2.3 --- Mosaic Floorplan --- p.30Chapter 2.3 --- Summary --- p.35Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37Chapter 3.1 --- Introduction --- p.37Chapter 3.2 --- Problem Formulation --- p.38Chapter 3.3 --- Previous Work --- p.38Chapter 3.4 --- Summary --- p.42Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44Chapter 4.1 --- Problem Formulation --- p.44Chapter 4.2 --- Previous Work --- p.45Chapter 4.2.1 --- Abutment Constraint --- p.45Chapter 4.2.2 --- Alignment Constraint --- p.49Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52Chapter 4.3 --- Summary --- p.53Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55Chapter 5.1 --- Introduction --- p.55Chapter 5.2 --- Problem Formulation --- p.56Chapter 5.3 --- Methodology --- p.57Chapter 5.3.1 --- Shape Validation --- p.58Chapter 5.3.2 --- Bus Ordering --- p.65Chapter 5.3.3 --- Floorplan Realization --- p.72Chapter 5.3.4 --- Simulated Annealing --- p.73Chapter 5.3.5 --- Soft Block Adjustment --- p.75Chapter 5.4 --- Experimental Results --- p.75Chapter 5.5 --- Summary --- p.77Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80Chapter 6.1 --- Introduction --- p.80Chapter 6.2 --- Problem Formulation --- p.81Chapter 6.3 --- The Representation --- p.82Chapter 6.3.1 --- Overview --- p.82Chapter 6.3.2 --- Review of TCG --- p.83Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84Chapter 6.3.4 --- Aligning Blocks --- p.85Chapter 6.3.5 --- Solution Perturbation --- p.87Chapter 6.4 --- Simulated Annealing --- p.92Chapter 6.5 --- Soft Block Adjustment --- p.92Chapter 6.6 --- Experimental Results --- p.93Chapter 6.7 --- Summary --- p.94Chapter 6.8 --- Acknowledgement --- p.95Chapter 7 --- Conclusion --- p.99Bibliography --- p.10

Efficient approaches in interconnect-driven floorplanning.

Lai Tsz Wai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 123-129).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- VLSI Design Cycle --- p.2Chapter 1.2 --- Physical Design Cycle --- p.4Chapter 1.3 --- Floorplanning --- p.7Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13Chapter 1.4 --- Motivations and Contributions --- p.17Chapter 1.5 --- Organization of this Thesis --- p.18Chapter 2 --- Literature Review on Floorplan Representation --- p.20Chapter 2.1 --- Slicing Floorplan Representation --- p.20Chapter 2.1.1 --- Normalized Polish Expression --- p.20Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21Chapter 2.2.1 --- Sequence Pair (SP) --- p.21Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23Chapter 2.2.3 --- O-tree --- p.25Chapter 2.2.4 --- B*-tree --- p.26Chapter 2.3 --- Mosaic Floorplan Representations --- p.28Chapter 2.3.1 --- Corner Block List (CBL) --- p.28Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32Chapter 2.4 --- Summary --- p.34Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37Chapter 3.1 --- Wirelength Estimation --- p.37Chapter 3.2 --- Congestion Optimization --- p.38Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48Chapter 3.3 --- Buffer Planning --- p.49Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63Chapter 3.4 --- Summary --- p.66Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68Chapter 4.1 --- Introduction --- p.68Chapter 4.2 --- Overview of Our Floorplanner --- p.70Chapter 4.3 --- Wire Density Model --- p.71Chapter 4.3.1 --- Computation of Ni --- p.72Chapter 4.3.2 --- Computation of Pi --- p.74Chapter 4.3.3 --- Usage of Mirror TBT --- p.76Chapter 4.4 --- Implementation --- p.76Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81Chapter 4.4.3 --- Cost Function --- p.81Chapter 4.4.4 --- Complexity --- p.81Chapter 4.5 --- Experimental Results --- p.82Chapter 4.6 --- Conclusion --- p.83Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85Chapter 5.1 --- Introduction --- p.85Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87Chapter 5.3 --- Overview of Our Floorplanner --- p.88Chapter 5.4 --- Buffer Planning --- p.89Chapter 5.4.1 --- Feasible Grids --- p.89Chapter 5.4.2 --- Table Look-up Approach --- p.89Chapter 5.5 --- Implementation --- p.91Chapter 5.5.1 --- Building the Look-up Tables --- p.91Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105Chapter 5.5.5 --- I/O Pin Locations --- p.106Chapter 5.5.6 --- Cost Function --- p.110Chapter 5.5.7 --- Complexity --- p.111Chapter 5.6 --- Experimental Results --- p.112Chapter 5.6.1 --- Selected Value for A --- p.112Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113Chapter 5.7 --- Conclusion --- p.116Chapter 6 --- Conclusion --- p.118Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120Bibliography --- p.12