7 research outputs found
Recommended from our members
Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs
For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs
Recommended from our members
Physics-Based Electromigration Modeling and Analysis and Optimization
Long-term reliability is a major concern in modern VLSI design. Literature has shown that reliability gets worse as technology advances. It is expected that the future VLSI systems would have shorter reliability-induced lifetime comparing with previous generations. Being one of the most serious reliability effects, electromigration (EM) is a physical phenomenon of the migration of metal atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change or open circuit and result in functional failure of the circuit. Power-ground networks are the most vulnerable part to EM effect among all the interconnect wires since the current flow on this part is the largest on the chip. With new generation oftechnology node and aggressive design strategies, more accurate and efficient EM models are required. However, traditional EM approaches are very conservative and cannot meet current aggressive design strategies. Besides circuit level, EM also need to be thoroughly studied in system level due to limited power and temperature budgets among cores on chip. This research focuses on developing physical level EM model for VLSI circuits and system level EM optimization for multi-core systems in order to overcome the aforementioned problems. Specifically, for physical level, we develop two EM immortality check methods and a power grid EM check method. Firstly, a voltage based EM immortality analysis has been developed. Immortality condition in nucleation phase can be determined fast and accurately for multi-segment interconnect wires. Secondly, a saturation volume based incubation phase immortality check method has been proposed. This method can further reduce the redundancy in VLSI circuit design by immortality check in multiphase. Furthermore, both immortality check methods are integrated into a new power grid EM check methodology (EMspice) as filter for EM analysis. These filters can accelerate the simulation by filtering out immortal trees so that we only need to do simulation on fewer trees that are mortal. Coupled EM simulation considering both hydrostatic stress and electronic current/voltage in the power grid network will be applied to these mortal trees. This tool can work seamlessly with commercial synthesis flow. Besides physical level reliability models, system level reliability optimization is also discussed in this research. A deep reinforcement learning based EM optimization has been proposed for multi-core system. Both long term reliability effect (hard error) and transient soft error are considered. Energy can be optimized with all the reliability and other constraints fast and accurately compared to existing reliability management techniques. Last but not least, a scheduling based reliability optimization method for multi-core systems has been proposed. NBTI, HCI and EM are considered jointly. Lifetime of the system can be improved significantly compared to traditional methods which mainly focus on utilization
Estudo da eletromigração em circuitos integrados na fase de projeto
Orientadores: Roberto Lacerda de Orio, Leandro Tiago ManeraTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O dano por eletromigração nas interconexões é um gargalo bem conhecido dos circuitos integrados, pois causam problemas de confiabilidade. A operação em temperaturas e densidades de corrente elevadas acelera os danos, aumentando a resistência da interconexão e, portanto, reduzindo a vida útil do circuito. Este problema tem se acentuado com o escalonamento da tecnologia. Para garantir a confiabilidade da interconexão e, como consequência, a confiabilidade do circuito integrado, métodos tradicionais baseados no chamado Efeito Blech e numa densidade de corrente máxima permitida são implementados durante o projeto da interconexão. Esses métodos, no entanto, não levam em consideração o impacto da eletromigração no desempenho do circuito. Neste trabalho, a abordagem tradicional é estendida e um método para avaliar o efeito da eletromigração no desempenho de circuito integrado é desenvolvido. O método é implementado em uma ferramenta que identifica as interconexões críticas em um circuito integrado e sugere larguras adequadas com base em diferentes critérios para mitigar os danos à eletromigração e aumentar a confiabilidade. Além disso, é determinada a variação dos parâmetros de desempenho do circuito conforme a resistência das interconexões aumenta. A ferramenta é incorporada ao fluxo de projeto do circuito integrado e usa os dados dos kits de projeto e relatórios diretamente disponíveis no ambiente de projeto. Uma análise precisa da distribuição de temperatura na estrutura de interconexão é essencial para uma melhor avaliação da confiabilidade da interconexão. Portanto, é implementado um modelo para calcular a temperatura em cada nível de metalização da estrutura de interconexão. A distribuição de temperatura nas camadas de metalização de diferentes tecnologias é investigada. É mostrado que a temperatura no Metal 1 da tecnologia Intel 10 nm aumenta 75 K, 12 K mais alta que no Metal 2. Como esperado, as camadas mais próximas dos transistores sofrem um aumento de temperatura mais significativo. A ferramenta é aplicada para avaliar eletromigração nas interconexões e na robustez de diferentes circuitos, como um oscilador em anel, um circuito gerador de tensão de referência tipo bandgap e um amplificador operacional. O amplificador operacional, em particular, é cuidadosamente estudado. A metodologia proposta identifica interconexões críticas que quando danificadas por eletromigração causam grandes variações no desempenho do circuito. No pior cenário, a frequência de corte do circuito varia 65% em 5 anos de operação. Uma descoberta interessante é que a metodologia proposta identifica interconexões críticas que não seriam identificadas pelos critérios tradicionais. Essas interconexões operam com densidades de corrente abaixo do limite recomendado pelas regras de projeto. No entanto, uma dessas interconexões leva a uma variação de 30% no ganho do amplificador operacional. Em resumo, a ferramenta proposta verificou que dos 20% de caminhos com uma densidade crítica de corrente, apenas 3% degradam significativamente o desempenho do circuito. Este trabalho traz o estudo da confiabilidade das interconexões e de circuitos integrados para a fase de projeto, o que permite avaliar a degradação do desempenho do circuito antecipadamente durante o seu desenvolvimento. A ferramenta desenvolvida permite ao projetista identificar interconexões críticas que não seriam detectadas usando o critério de densidade máxima de corrente, levando a uma análise mais ampla e precisa da robustez de circuitos integradosAbstract: Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, because it causes reliability problems. Operation at high temperatures and current densities accelerates the damage, increasing the interconnect resistance and, therefore, reducing the circuit lifetime. This issue has been accentuated with the technology downscaling. To guarantee the interconnect reliability and, as a consequence, the integrated circuit reliability, traditional methods based on the so-called Blech Effect and on the maximum allowed current density are implemented during interconnect design. These methods, however, do not take into account the impact of the electromigration on the circuit performance. In this work the traditional approach is extended and a method to evaluate the effect of the electromigration in an integrated circuit performance is developed. The method is implemented in a tool which identifies the critical interconnect lines of an integrated circuit and suggests the proper interconnect width based on different criteria to mitigate the electromigration damage and to increase the reliability. In addition, the variation of performance parameters of the circuit as an interconnect resistance changes is determined. The tool is incorporated into the design flow of the integrated circuit and uses the data from design kits and reports directly available from the design environment. An accurate analysis of the temperature distribution on the interconnect structure is essential to a better assessment of the interconnect reliability. Therefore, a model to compute the temperature on each metallization level of the interconnect structure is implemented. The temperature distribution on the metallization layers of different technologies is investigated. It is shown that the temperature in the Metal 1 of the Intel 10 nm can increase by 75 K, 12 K higher than in the Metal 2. As expected, the layers that are closer to the transistors undergo a more significant temperature increase. The tool is applied to evaluate the interconnects and the robustness of different circuits, namely a ring oscillator, a bandgap voltage reference circuit, and an operational amplifier, against electromigration. The operational amplifier, in particular, is thoroughly studied. The proposed methodology identifies critical interconnects which under electromigration cause large variations in the performance of the circuit. In a worst-case scenario, the cutoff frequency of the circuit varies by 65% in 5 years of operation. An interesting finding is that the proposed methodology identifies critical interconnects which would not be identified by the traditional criteria. These interconnects have current densities below the limit recommended by the design rules. Nevertheless, one of such an interconnect leads to a variation of 30% in the gain of the operational amplifier. In summary, the proposed tool verified that from the 20% paths with a critical current density, only 3% degrades significantly the circuit performance. This work brings the study of the reliability of the interconnects and of integrated circuits to the design phase, which provides the assessment of a circuit performance degradation at an early stage of development. The developed tool allows the designer to identify critical interconnects which would not be detected using the maximum current density criterion, leading to more accurate analysis of the robustness of integrated circuitsDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétrica88882.329437/2019-01CAPE
Dependable Embedded Systems
This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems
Cu(Ag)-Legierungsschichten als Werkstoff für Leiterbahnen höchstintegrierter Schaltkreise: Herstellung, Gefüge, thermomechanische Eigenschaften, Elektromigrationsresistenz
Die vorliegende Arbeit verfolgt das Ziel, Cu(Ag)-Dünnschichten als potentiellen Werkstoff für Leiterbahnen in der Mikroelektronik zu untersuchen. Für die Beurteilung dieses Materialsystems wurden vier Schwerpunkte bezüglich der Schichtcharakterisierung definiert: Herstellung, Gefüge, thermomechanische Eigenschaften, Elektromigrationsresistenz. Grundlage sämtlicher Untersuchungen ist eine geeignete Probenpräparation. In Anlehnung an Technologien, die zur Zeit bei der Herstellung von reinen Cu-Leiterbahnen Anwendung finden, erfolgte die Beschichtung der Cu(Ag)-Schichten (Dicke bis 1 µm) galvanisch aus einem schwefelsauren Elektrolyten unter Additiveinsatz auf thermisch oxidierten Siliziumwafern. Hierbei war nicht nur die Abscheidung von ganzflächigen Dünnschichten, sondern auch die Beschichtung auf strukturierte Substrate von Interesse. Die erzeugten Schichtproben werden in ihren Gefügeeigenschaften, vergleichend zu reinen Kupferschichten, charakterisiert. Hierzu zählen Korngrößen und -orientierungen, thermisches Gefügeverhalten, Einbau, Verteilung und Segregation von Silber und Fremdstoffen sowie die elektrischen Eigenschaften. Von grundsätzlicher Bedeutung für das Elektromigrationsverhalten und damit für die Zuverlässigkeit und das Leistungsvermögen sind die thermomechanischen Eigenschaften. Diese werden an ausgedehnten Schichten mit der Substratkrümmungsmessung bis zu Temperaturen von 500°C beschrieben. Die Diskussion des mechanischen Schichtverhaltens umfasst sowohl thermische als auch temporale Charakteristika. Die Untersuchungen geben einen Einblick in die wirkenden Mechanismen des Stofftransports und des Spannungsabbaus. Den Abschluss der Arbeit stellen erste Experimente zum Elektromigrationsverhalten der Cu(Ag)-Dünnschichten dar. Den Kern dieser Analysen bilden Messungen an sog. Blech-Strukturen (Materialdriftexperimente). Hierbei werden geeignete Technologien für die mikrotechnologische Herstellung von derartigen Cu(Ag)-Strukturen vorgestellt. Anhand erster Messungen wird das Elektromigrationsverhalten von Cu(Ag)-Metallisierungen in seinen Grundcharakteristika beschrieben