Relevance of First-Tier, Peer-Reviewed Journals in the Tenure and Promotion Process at Non-Doctoral Granting Engineering Institutions

ABSTRACT The IEEE (formerly the Institute of Electrical and Electronics Engineers) is the world's largest professional society dedicated to the advancement of technology. While it is indeed growing into multiple technology areas, the IEEE is still first an organization of electrical, electronics, and computer engineering professionals. It has over 400,000 members and publishes nearly 100, first-tier, peer-reviewed journals. As such a large purveyor of scholarly works, engineering faculty at almost all academic institutions (doctoral granting and non-doctoral granting) are familiar with the IEEE. For this reason, the IEEE makes an excellent case study for the relevance of first-tier, peer-reviewed journals in the tenure and promotion process at non-doctoral granting engineering institutions. In our work, we surveyed editors of the 97 IEEE journals. 93% of respondents indicated that 10% or less of their submissions were from nonacademic institutions. None (0%) of the respondents believed that the number of non-doctoral granting institution submissions would be increasing over the next three years. In fact, a majority of the respondents (55%) see the number of nondoctoral granting institution submissions decreasing in the same time frame. To correlate this data, we examined a sample of 2,099 articles published in the first issue of each IEEE journal in 2009. 357 (17%) of these 2,099 articles were authored by individuals from academic institutions in the United States. Of the 357, only 35 were published by individuals from nondoctoral granting institutions (1.7%), with only 8 (0.38%) from institutions where a bachelor degree is the highest offered

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well as for improving overall system performance. It is a major challenge to introduce cache reconfiguration into real-time embedded systems since dynamic analysis may adversely affect tasks with real-time constraints. This paper presents a novel approach for implementing cache reconfiguration in soft real-time systems by efficiently leveraging static analysis during execution to both minimize energy and maximize performance. To the best of our knowledge, this is the first attempt to integrate dynamic cache reconfiguration in real-time scheduling techniques. Our experimental results using a wide variety of applications have demonstrated that our approach can significantly (up to 74%) reduce the overall energy consumption of the cache hierarchy in soft real-time systems. 1

Fast configurable-cache tuning with a unified second-level cache

Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or a second level with separate instruction and data configurable caches. We instead use a commercially-common unified second level, a seemingly minor difference that actually expands the configuration space from 500 to about 20,000. We develop additive way tuning for tuning a cache subsystem with this large space, yielding 62% energy savings and 35% performance improvements over a non-configurable cache, greatly outperforming an extension of a previous method

Application-Specific Memory Subsystems

The disparity in performance between processors and main memories has led computer architects to incorporate large cache hierarchies in modern computers. These cache hierarchies are designed to be general-purpose in that they strive to provide the best possible performance across a wide range of applications. However, such a memory subsystem does not necessarily provide the best possible performance for a particular application. Although general-purpose memory subsystems are desirable when the work-load is unknown and the memory subsystem must remain fixed, when this is not the case a custom memory subsystem may be beneficial. For example, in an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA) designed to run a particular application, a custom memory subsystem optimized for that application would be desirable. In addition, when there are tunable parameters in the memory subsystem, it may make sense to change these parameters depending on the application being run. Such a situation arises today with FPGAs and, to a lesser extent, GPUs, and it is plausible that general-purpose computers will begin to support greater flexibility in the memory subsystem in the future. In this dissertation, we first show that it is possible to create application-specific memory subsystems that provide much better performance than a general-purpose memory subsystem. In addition, we show a way to discover such memory subsystems automatically using a superoptimization technique on memory address traces gathered from applications. This allows one to generate a custom memory subsystem with little effort. We next show that our memory subsystem superoptimization technique can be used to optimize for objectives other than performance. As an example, we show that it is possible to reduce the number of writes to the main memory, which can be useful for main memories with limited write durability, such as flash or Phase-Change Memory (PCM). Finally, we show how to superoptimize memory subsystems for streaming applications, which are a class of parallel applications. In particular, we show that, through the use of ScalaPipe, we can author and deploy streaming applications targeting FPGAs with superoptimized memory subsystems. ScalaPipe is a domain-specific language (DSL) embedded in the Scala programming language for generating streaming applications that can be implemented on CPUs and FPGAs. Using the ScalaPipe implementation, we are able to demonstrate actual performance improvements using the superoptimized memory subsystem with applications implemented in hardware

GreenC5: An Adaptive, Energy-Aware Collection for Green Software Development

Dynamic data structures in software applications have been shown to have a large impact on system performance. In this paper, we explore energy saving opportunities of interface-based dynamic data structures. Our results suggest that savings opportunities exist in the C5 Collection between 16.95% and 97.50%. We propose a prototype and architecture for creating adaptive green data structures by applying machine learning tools to build a model for predicting energy efficient data structures based on the dynamic workload. Our neural network model can classify energy efficient data structures based on features such as the number of elements, frequency of operations, interface and set/bag semantics. The 10-fold cross validation result show 95.80% average accuracy of these predictions. Our n-gram model can accurately predict the most energy efficient data structure sequence in 19 simulated and real-world programs - on average, with more than 50% accuracy and up to 98% using a bigram predictor. Our GreenC5 prototype demonstrates how a green data structure can be implemented. With a simple decision making technique, the data structure can efficiently adapt for energy efficiency with low overhead. The median of GreenC5\u27s potential energy savings is more than 60% and ranges from 18% to 95%

A communication-driven routing technique for application-specific NoCs

The final publication is available at Springer via http://dx.doi.org/10.1007/s10766-010-0159-9Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the reduction of both area and power dissipation. As a result, two-dimensional meshes have become the preferred topology, since it offers low and constant link delay. Unfortunately, manufacturing defects or even real-time failures often make the resulting topology to become irregular, preventing the use of traditional routing algorithms. This scenario shows the need for topology-agnostic routing algorithms that provide a valid routing solution when applied over any topology. This paper proposes a new communication-driven routing technique that optimizes the network performance for Application-Specific NoCs. This technique combines a flexible, topology-agnostic routing algorithm with a communication-aware mapping technique that matches the traffic generated by the application with the available network bandwidth. Since the mapping technique can be pruned as needed in order to fit either quality function values or time constraints, this technique can be adapted to fit with different computational costs. The evaluation results show that it significantly improves network performance in terms of both latency and power consumption.This work has been jointly supported by the Spanish MICINN, the European Commission FEDER funds, and the University of Valencia under grants Consolider-Ingenio 2010 CSD2006-00046, TIN2009-14475-C04-04, and V_SEGLES_PIE.Tornero, R.; Orduña Huertas, JM.; Mejia, A.; Flich Cardo, J.; Duato Marín, JF. (2011). A communication-driven routing technique for application-specific NoCs. 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