485 research outputs found
High-Level Synthesis of Pipelined FSM from Loop Nests
Embedded systems raise many challenges in power, space and speed efficiency. The current trend is to build heterogeneous systems on a chip with specialized processors and hardware accelerators. Generating an hardware accelerator from a computational kernel requires a deep reorganization of the code and the data. Typically, parallelism and memory bandwidth are met thanks to fine-grain loop transformations. Unfortunately, the resulting control automaton is often very complex and eventually bound the circuit frequency, which limits the benefits of the optimization. This is a major lock, which strongly limits the power of the code optimizations applicable by high-level synthesis tools.In this report, we propose an architecture of control automaton and an algorithm of high-level synthesis which translates efficiently the control required by fine-grain loop optimizations. Unlike the previous approaches, our control automaton can be pipelined at will, without any restriction. Hence, the frequency of the automaton can be as high as possible. Experimental results on FPGA confirms that our control circuit can reach a high frequency with a reasonable resource consumption
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Silicon compilation
Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory
FPGA-Based Bandwidth Selection for Kernel Density Estimation Using High Level Synthesis Approach
FPGA technology can offer significantly hi\-gher performance at much lower
power consumption than is available from CPUs and GPUs in many computational
problems. Unfortunately, programming for FPGA (using ha\-rdware description
languages, HDL) is a difficult and not-trivial task and is not intuitive for
C/C++/Java programmers. To bring the gap between programming effectiveness and
difficulty the High Level Synthesis (HLS) approach is promoting by main FPGA
vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU
architectures, but can also be successfully performed using HLS approach. In
the paper we implement a bandwidth selection algorithm for kernel density
estimation (KDE) using HLS and show techniques which were used to optimize the
final FPGA implementation. We are also going to show that FPGA speedups,
comparing to highly optimized CPU and GPU implementations, are quite
substantial. Moreover, power consumption for FPGA devices is usually much less
than typical power consumption of the present CPUs and GPUs.Comment: 23 pages, 6 figures, extended version of initial pape
A proposed synthesis method for Application-Specific Instruction Set Processors
Due to the rapid technology advancement in integrated circuit era, the need for the high computation
performance together with increasing complexity and manufacturing costs has raised the demand for
high-performance con
fi
gurable designs; therefore, the Application-Speci
fi
c Instruction Set Processors
(ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a
commonly used technique, but the automated hardware model generation is less frequently applied in
terms of
fi
nal RTL implementations. Contrary to this, the
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nal register-transfer level models are usually
created, at least partly, manually. This paper presents a novel approach for automated hardware model
generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language
(Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The
proposed AMDL-based pre-synthesis method is based on a set of pre-de
fi
ned VHDL implementation
schemes, which ensure the qualities of the automatically generated register-transfer level models in
terms of resource requirement and operation frequency. The design framework implementing the
algorithms required by the synthesis method is also presented
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