Low-complexity RLS algorithms using dichotomous coordinate descent iterations

In this paper, we derive low-complexity recursive least squares (RLS) adaptive filtering algorithms. We express the RLS problem in terms of auxiliary normal equations with respect to increments of the filter weights and apply this approach to the exponentially weighted and sliding window cases to derive new RLS techniques. For solving the auxiliary equations, line search methods are used. We first consider conjugate gradient iterations with a complexity of O(N-2) operations per sample; N being the number of the filter weights. To reduce the complexity and make the algorithms more suitable for finite precision implementation, we propose a new dichotomous coordinate descent (DCD) algorithm and apply it to the auxiliary equations. This results in a transversal RLS adaptive filter with complexity as low as 3N multiplications per sample, which is only slightly higher than the complexity of the least mean squares (LMS) algorithm (2N multiplications). Simulations are used to compare the performance of the proposed algorithms against the classical RLS and known advanced adaptive algorithms. Fixed-point FPGA implementation of the proposed DCD-based RLS algorithm is also discussed and results of such implementation are presented

Rendering PostScript^TM fonts on FPGAs

This paper describes how custom computing machines can be used to implement a simple outline font processor. An FPGA based co-processor is used to accelerate the compute intensive portions of font rendering. The font processor builds on several PostScript components previously presented by the authors to produce a system that can rapidly render fonts. A prototype implementation is described followed by an explanation of how this could be extended to build a complete system

Alternative implementations of a fractional order control algorithm on FPGAs

Traditionally, microprocessor and digital signal processors have been used extensively in controlling simple processes, such as direct current motors. The Field Programmable Gate Arrays (FPGA) are currently emerging as an alternative to the previously used devices in controlling all sorts of processes. The fractional order proportional-integrative control algorithm has the advantage of enhancing the closed loop performance as compared to traditional proportional-integrative controllers, but the implementation requires a higher number of computations. Implementations of control algorithms on FPGAs are nowadays much faster than implementations on microprocessors. This allows for a more accurate digital realization of the fractional order controller. The paper presents nine alternative implementations of such control algorithm on two different FPGA targets. The experimental results, considering DC motor speed control, show that double, fixed-point and integer data representation may be used efficiently for control purposes