Power efficient and high performance VLSI architecture for AES algorithm

AbstractAdvanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay

Analisis Perbandingan Algoritma AES Dan RC4 Pada Enkripsi dan Dekripsi Data Teks Berbasis CrypTool 2

The development of technology is followed by a large amount of data. Not all of the data is presented to the general public, some data are strictly kept confidential because of certain interests. This study aims to test the encryption and decryption of text data (with *.txt format) to maintain confidentiality and compare the performance of the AES algorithm with RC4. This study uses the AES and RC4 algorithms with a key length of 256 bits using CrypTool 2 for encryption and decryption processes. The result of the first trial is that the encryption and decryption test of the AES algorithm on text data results in a different ciphertext size from the original text data. While the second trial was carried out by encryption and decryption of the RC4 algorithm on text data, resulting in the same ciphertext size before the simulation process was carried out. So from this research, the RC4 algorithm produces a smaller ciphertext size than using the AES algorithm.Berkembangnya teknologi diikuti dengan bertambahnya data yang cukup besar. Data tersebut tidak semuanya disajikan untuk khalayak umum, beberapa data sangat dijaga kerahasiannya karena kepentingan tertentu. Penelitian ini bertujuan untuk melakukan uji coba enkripsi dan dekripsi pada data teks (dengan  format  *.txt)  untuk menjaga kerahasiannya dan membandingkan kinerja dari algoritma AES dengan RC4. Penelitian ini menggunakan metode algoritma AES dan RC4 dengan panjang kunci 256 bit menggunakan CrypTool 2  untuk proses enkripsi dan dekripsi. Hasilnya uji coba pertama yaitu dilakukan uji coba enkripsi dan dekripsi algortima AES pada data teks menghasilkan ukuran ciphertext yang berbeda dari data teks asli. Sedangkan uji coba kedua dilakukan enkripsi dan dekripsi algoritma RC4 pada data teks dihasilkan ukuran ciphertext yang sama sebelum dilakukan proses simulasi. Sehingga dari penelitian ini diperoleh algoritma RC4 menghasilkan ukuran ciphertext lebih kecil dari pada menggunakan algoritma AES

FPGA Implementation of Advanced Encryption Standard

Security is a crucial parameter to be recognized with the improvement of electronic communication. Today most research in the field of electronic communication includes look into on security concern of communication. At present most by and large consumed and recognized standard for encryption of data is the Advanced Encryption Standard. AES was transformed to supplant the developing Data Encryption Standard. The AES calculation is fit for handling cryptographic keys which are of 256, 128, & 192 bits to encode & unscramble data in squares of 128 bits. The center of the calculation is made up of four key parts, which manage 8 bit data pieces. The whole 128 bit data to the calculation is dealt with into a 4 x 4 grid termed a state, to obtain the 8 bit square. Considering the complex nature of advance encryption standard (AES) algorithm, it requires a huge amount of hardware resources for its practical implementation. The extreme amount of hardware requirement makes its hardware implementation very burdensome. During this research, a FPGA scheme is introduced which is highly efficient in terms of resource utilization. In this scheme implementation of AES algorithm is done as a finite state machine (FSM). VHDL is used as a programming language for the purpose of design. Data path and control unit are designed for both cipher and decipher block, after that respective data path and control unit are integrated using structural modeling style of VHDL. Xilinx_ISE_14.2 software is being used for the purpose of simulating and optimizing the synthesizable VHDL code. The working of the implemented algorithm is tested using VHDL test bench wave form of Xilinx ISE simulator and resource utilization is also presented for a targeted Spartan3e XC3s500e FPGA

VLSI implementation of AES algorithm

In the present era of information processing through computers and access of private information over the internet like bank account information even the transaction of money, business deal through video conferencing, encryption of the messages in various forms has become inevitable. There are mainly two types of encryption algorithms, private key (also called symmetric key having single key for encryption and decryption) and public key (separate key for encryption and decryption). In the present work, hardware optimization for AES architecture has been done in different stages. The hardware comparison results show that as AES architecture has critical path delay of 9.78 ns when conventional s-box is used, whereas it has critical path delay of 8.17 ns using proposed s-box architecture. The total clock cycles required to encrypt 128 bits of data using proposed AES architecture are 86 and therefore, throughput of the AES design in Spartan-6 of Xilinx FPGA is approximately 182.2 Mbits/s. To achieve the very high speed, full custom design of s-box in composite field has been done for the proposed s-box architecture in Cadence Virtuoso. The novel XOR gate is proposed for use in s-box design which is efficient in terms of delay and power along with high noise margin. The implementation has been done in 180 nm UMC technology. Total dynamic power in the proposed XOR gate is 0.63 µW as compared to 5.27 µW in the existing design of XOR. The designed s-box using proposed XOR occupies a total area of 27348 µm2. The s-box chip consumes 22.6 µW dynamic power and has 8.2 ns delay after post layout simulation has been performed