Embedded Dsp Based License Plate Localization

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2008Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2008Bu çalışmada sözü edilen ve tasarlanan plaka yer saptama uygulaması sayısal sinyal işleme tabanlı gömülü bir mimari üzerinde gerçek zamanlı görüntü işleme kıstaslarına uyularak oluşturulan, ilgi duyulan bir konudur ve trafik yönetimi, gümrük kontrolleri, otoyol ödeme sistemleri, çalıntı arabaların tanınması, park yerleri, yasak bölgelerin kontrolü gibi birçok uygulama alanında gerek duyulan tam işlevli ve özdevimli tanıma sistemlerinin ayırt edici bir özelliğidir. Komple tanıma sisteminin ayırt edici bir parçası olmasının nedeni bir kez plaka yeri doğru olarak saptandığında aslında sorunun tanıma aşamasına indirgenmesidir. Tanıma biriminin girişinde yer alması ile başarımındaki kazancı iyileştirme sorununun ötesinde, bilinen bilgisayar tabanlı sistemlerle karşılaştırıldığında uygulamasının işlevine göre dar hacimli, kolay taşınabilir, düşük enerji tüketimli, ve düşük maliyetli mimariye sahip bir görüntü gözetim sisteminin parçası olması öncelikli bir durumdur. İşlemsel süreçlerde, sistem tasarım ve geliştirme aşamalarında tüm bu kısıtlamaların göz önünde tutulması amaçlanmıştır.Yer saptama işlemsel süreci genel olarak ayrıt bulma, eşikleme, bağlı bileşen etiketleme, plaka karakterlerini saran dikdörtgenlerin, ve son olarak da giriş görüntüsündeki plaka yerinin belirlenmesi aşamalarından oluşur. Öngörüldüğü şekliyle, tümleşik devrenin kullanışlı, yetkin, karmaşık, ve çok işlevli paralel çalışan komutları ile yüksek başarımlı doğrudan bellek erişimi, genel amaçlı giriş, çıkış ve çok çekirdekli yapısından faydalınarak plaka yer saptama işlemsel sürecinin geliştirilmesine ek olarak, sayısal işaret işleme tabanlı gömülü gerçek zamanlı bir görüntü izleme sistemi tipik bilgisayar tabanlı sistemlerle kıyaslandığında hem başarım hem verimlilik açısından gereksinimleri oldukça karşılayacak şekilde tasarlanmış ve geliştirilmiştir.The system presented and designed in this work as an embedded DSP architecture corresponding to real time video processing constraints is an application of license plate localization which is a challenging issue and distinctive unit of full featured and considerably standardized automated recognition systems required in several application areas like traffic management, custom controls, toll-pay systems, identification of stolen cars, parking, controlling of restricted zones. The reason of the fact it is a distinctive part of overall recognition system is that the issue is basically reduced to a recognition stage once the location of the license plate is correctly found. Beyond the reason that it is an issue to enhance the performance gain as a very important milestone prior to recognition modules, it is a priority task as a part of typical video surveillance system that the application should propose compact design, portability, low power consumption and low cost architecture as compared with generic personal computer based systems. It is aimed to consider all these constraints in algorithm and system design and development. Localization Algorithm generally consists of edge detection, threshold, component labeling, determination of surrounding rectangles of plate characters candidates, and finally localization of the plate in an input image. As contemplated, a DSP based embedded real-time video surveillance system is designed and developed comparatively sufficient to generic computer based systems in resolutions of both performance and efficiency constraints in addition to license plate localization algorithm development by utilizing flexible, powerful, complex multifunction instructions, high performance direct memory access and general purpose input outputs and multi core structures of integrated DSP.Yüksek LisansM.Sc

Vehicle license plate detection and recognition

"December 2013.""A Thesis presented to the Faculty of the Graduate School at the University of Missouri In Partial Fulfillment of the Requirements for the Degree Master of Science."Thesis supervisor: Dr. Zhihai He.In this work, we develop a license plate detection method using a SVM (Support Vector Machine) classifier with HOG (Histogram of Oriented Gradients) features. The system performs window searching at different scales and analyzes the HOG feature using a SVM and locates their bounding boxes using a Mean Shift method. Edge information is used to accelerate the time consuming scanning process. Our license plate detection results show that this method is relatively insensitive to variations in illumination, license plate patterns, camera perspective and background variations. We tested our method on 200 real life images, captured on Chinese highways under different weather conditions and lighting conditions. And we achieved a detection rate of 100%. After detecting license plates, alignment is then performed on the plate candidates. Conceptually, this alignment method searches neighbors of the bounding box detected, and finds the optimum edge position where the outside regions are very different from the inside regions of the license plate, from color's perspective in RGB space. This method accurately aligns the bounding box to the edges of the plate so that the subsequent license plate segmentation and recognition can be performed accurately and reliably. The system performs license plate segmentation using global alignment on the binary license plate. A global model depending on the layout of license plates is proposed to segment the plates. This model searches for the optimum position where the characters are all segmented but not chopped into pieces. At last, the characters are recognized by another SVM classifier, with a feature size of 576, including raw features, vertical and horizontal scanning features. Our character recognition results show that 99% of the digits are successfully recognized, while the letters achieve an recognition rate of 95%. The license plate recognition system was then incorporated into an embedded system for parallel computing. Several TS7250 and an auxiliary board are used to simulIncludes bibliographical references (pages 67-73)

Efficient arithmetic for high speed DSP implementation on FPGAs

The author was sponsored by EnTegra Ltd, a company who develop hardware and software products and services for the real time implementation of DSP and RF systems. The field programmable gate array (FPGA) is being used increasingly in the field of DSP. This is due to the fact that the parallel computing power of such devices is ideal for today’s truly demanding DSP algorithms. Algorithms such as the QR-RLS update are computationally intensive and must be carried out at extremely high speeds (MHz). This means that the DSP processor is simply not an option. ASICs can be used but the expense of developing custom logic is prohibitive. The increased use of the FPGA in DSP means that there is a significant requirement for efficient arithmetic cores that utilises the resources on such devices. This thesis presents the research and development effort that was carried out to produce fixed point division and square root cores for use in a new Electronic Design Automation (EDA) tool for EnTegra, which is targeted at FPGA implementation of DSP systems. Further to this, a new technique for predicting the accuracy of CORDIC systems computing vector magnitudes and cosines/sines is presented. This work allows the most efficient CORDIC design for a specified level of accuracy to be found quickly and easily without the need to run lengthy simulations, as was the case before. The CORDIC algorithm is a technique using mainly shifts and additions to compute many arithmetic functions and is thus ideal for FPGA implementation

Χρήση μοντέλου παράλληλου προγραμματισμού για σύνθεση αρχιτεκτονικών

The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this Dissertation we introduce a methodology to automatically synthesize hardware accelerators from OpenCL applications. OpenCL is a recent industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our methodology maps OpenCL kernels into hardware accelerators based on architectural templates that explicitly decouple computation from memory communication whenever this is possible. The templates can be tuned to provide a wide repertoire of accelerators that meet user performance requirements and FPGA device characteristics. Furthermore a set of high- and low-level compiler optimizations is applied to generate optimized accelerators. Our experimental evaluation shows that the generated accelerators are tuned efficiently to match the applications memory access pattern and computational complexity and to achieve user performance requirements. An important objective of our tool is to expand the FPGA development user base to software engineers thereby expanding the scope of FPGAs beyond the realm of hardware design.To πρόβλημα της αυτόματης δημιουργίας μονάδων υλικό από παραστάσεις υψηλού επιπέδου εφαρμογής είναι στην πρώτη γραμμή της EDA έρευνας κατά τη διάρκεια των τελευταίων ετών. Σε αυτή την διατριβή παρουσιάζουμε μια μεθοδολογία για τη αυτόματη σύνθεση επιταχυντές υλικού από εφαρμογές OpenCL. OpenCL είναι ένα πρόσφατο πρότυπο για τη σύνταξη των προγραμμάτων που εκτελούνται σε πλατφόρμες πολλαπλών πυρήνων και επιταχυντές όπως GPUs. Η μεθοδολογία μας μετατρέπει προγράμματα OpenCL σε επιταχυντές υλικού με βάση αρχιτεκτονικά πρότυπα που ρητά αποσυνδέει τους υπολογισμούς από την μεταφορά δεδομένων από/προς την μνήμη όποτε αυτό είναι δυνατό. Τα πρότυπα μπορούν να συντονιστούν ώστε να παρέχουν ένα ευρύ ρεπερτόριο από επιταχυντές που πληρούν τις απαιτήσεις απόδοσης των χρηστών και τα χαρακτηριστικά της συσκευής FPGA. Επιπλέον ένα σύνολο υψηλής και χαμηλής στάθμης βελτιστοποιήσεις μεταγλωττιστή εφαρμόζεται για να παράγει βελτιστοποιημένα επιταχυντές. Η πειραματική αξιολόγηση δείχνει ότι οι επιταχυντές που δημιουργούνται αποτελεσματικά συντονισμένοι για να ταιριάζει με το μοτίβο πρόσβασης στην μνήμη κάθε εφαρμογής και την υπολογιστική πολυπλοκότητα και να επιτύχουν τις απαιτήσεις απόδοσης των χρηστών. Ένας σημαντικός στόχος του εργαλείου μας είναι η επέκταση της βάσης χρηστών πλατφόρμες FPGA για μηχανικούς λογισμικού ώστε να γίνει ανάπτυξη FPGA συστήματα από μηχανικούς λογισμικού χωρίς την ανάγκη για εμπειρία σχεδιασμού υλικού