1,127 research outputs found
Building Blocks for Spikes Signals Processing
Neuromorphic engineers study models and
implementations of systems that mimic neurons behavior in the
brain. Neuro-inspired systems commonly use spikes to
represent information. This representation has several
advantages: its robustness to noise thanks to repetition, its
continuous and analog information representation using digital
pulses, its capacity of pre-processing during transmission time,
... , Furthermore, spikes is an efficient way, found by nature, to
codify, transmit and process information. In this paper we
propose, design, and analyze neuro-inspired building blocks
that can perform spike-based analog filters used in signal
processing. We present a VHDL implementation for FPGA.
Presented building blocks take advantages of the spike rate
coded representation to perform a massively parallel processing
without complex hardware units, like floating point arithmetic
units, or a large memory. Those low requirements of hardware
allow the integration of a high number of blocks inside a FPGA,
allowing to process fully in parallel several spikes coded signals.Junta de Andalucía P06-TIC-O1417Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach
This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture
A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
This paper presents a new architecture, design
flow, and field-programmable gate array (FPGA) implementation
analysis of a neuromorphic binaural auditory sensor, designed
completely in the spike domain. Unlike digital cochleae that
decompose audio signals using classical digital signal processing
techniques, the model presented in this paper processes information
directly encoded as spikes using pulse frequency modulation
and provides a set of frequency-decomposed audio information
using an address-event representation interface. In this case,
a systematic approach to design led to a generic process for
building, tuning, and implementing audio frequency decomposers
with different features, facilitating synthesis with custom features.
This allows researchers to implement their own parameterized
neuromorphic auditory systems in a low-cost FPGA in order to
study the audio processing and learning activity that takes place
in the brain. In this paper, we present a 64-channel binaural
neuromorphic auditory system implemented in a Virtex-5 FPGA
using a commercial development board. The system was excited
with a diverse set of audio signals in order to analyze its response
and characterize its features. The neuromorphic auditory system
response times and frequencies are reported. The experimental
results of the proposed system implementation with 64-channel
stereo are: a frequency range between 9.6 Hz and 14.6 kHz
(adjustable), a maximum output event rate of 2.19 Mevents/s,
a power consumption of 29.7 mW, the slices requirements
of 11 141, and a system clock frequency of 27 MHz.Ministerio de Economía y Competitividad TEC2012-37868-C04-02Junta de Andalucía P12-TIC-130
Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach
This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.Peer reviewe
FPGA based secure and noiseless image transmission using LEA and optimized bilateral filter
In today’s world, the transmission of secured and noiseless image is a difficult task. Therefore, effective strategies are important to secure the data or secret image from the attackers. Besides, denoising approaches are important to obtain noise-free images. For this, an effective crypto-steganography method based on Lightweight Encryption Algorithm (LEA) and Modified Least Significant Bit (MLSB) method for secured transmission is proposed. Moreover, a bilateral filter-based Whale Optimization Algorithm (WOA) is used for image denoising. Before image transmission, the secret image is encrypted by the LEA algorithm and embedded into the cover image using Discrete Wavelet Transform (DWT) and MLSB technique. After the image transmission, the extraction process is performed to recover the secret image. Finally, a bilateral filter-WOA is used to remove the noise from the secret image. The Verilog code for the proposed model is designed and simulated in Xilinx software. Finally, the simulation results show that the proposed filtering technique has superior performance than conventional bilateral filter and Gaussian filter in terms of Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM)
High-Speed and Low-Cost Implementation of Explicit Model Predictive Controllers
This paper presents a new form of piecewise-affine (PWA) solution, referred to as PWA hierarchical (PWAH), to approximate the explicit model predictive control (MPC) law, achieving a very rapid control response with the use of very few computational and memory resources. This is possible because PWAH controllers consist of single-input single-output PWA modules connected in cascade so that the parameters needed to define them increase linearly instead of exponentially with the input dimension of the control problem. PWAH controllers are not universal approximators but several explicit MPC controllers can be efficiently approximated by them. A methodology to design PWAH controllers is presented and validated with application examples already solved by MPC approaches. The designed PWAH controllers implemented in field-programmable gate arrays provide the highest control speed using the fewest resources compared with the other digital implementations reported in the literature.Ministerio de Economía, Industria y Competitividad TEC2014-57971-
FPGA implementation of bluetooth low energy physical layer with OpenCL
Aquesta dissertació presenta principalment el disseny de processament digital de senyals (DSP) entre la transmissió en Capa Física de Bluetooth de Baixa Energia (BLE PHY), i la seva implementació en dispositius Field Programmable Gate Array (FPGA) utilitzant Open Computing Language (OpenCL). Durant el disseny de DSP, es basa en l'arquitectura en fase / quadratura-fase (IQ) per construir els processos de modulació i demodulació del senyal mitjançant l'ús d'un esquema de modelador de senyal anomenat Gaussian Frequency-Shift Keying (GFSK), en la comunicació de curt abast que presenta un fort rendiment anti-interferència. Pel que fa a l'OpenCL, és un dels mètodes de síntesi d'alt nivell (HLS) per al disseny de FPGA. No només compta amb una alta productivitat, sinó que també pot realitzar una alta eficiència operativa per FPGA mitjançant l'ús d'arquitectura de programació paral·lela. A més, aquí invoca una plataforma remota anomenada Intel DevCloud per controlar el FPGA per verificar el programa, faria que el disseny fos més còmode i econòmic.Esta disertación presenta principalmente el diseño de Procesamiento Digital de Señales (DSP) entre la transmisión en Bluetooth Low Energy Physical Layer (BLE PHY), y su implementación en Field Programmable Gate Array (FPGA) con Open Computing Language (OpenCL). Durante el diseño de DSP, se basa en la arquitectura In-Phase/Quadrature-Phase (IQ) para construir los procesos de modulación y demodulación de la señal mediante la utilización de un esquema de modelador de señal llamado Gaussian Frequency-Shift Keying (GFSK), en la comunicación de corto alcance presenta un fuerte rendimiento anti-interferencia. Con respecto al OpenCL, es uno de los métodos de síntesis de alto nivel (HLS) para el diseño de FPGA. No solo presenta una alta productividad, sino que también puede lograr una alta eficiencia operativa para FPGA mediante el uso de la arquitectura de programación paralela. Además, aquí invoca una plataforma remota llamada Intel DevCloud para controlar la FPGA para verificar el programa, lo que haría que el diseño fuera más conveniente y económico.This dissertation is primarily presenting the design of Digital Signal Processing (DSP) between the transmission in Bluetooth Low Energy Physical Layer (BLE PHY), and its implementation in a Field Programmable Gate Array (FPGA) device with Open Computing Language (OpenCL). During the design of DSP, it bases on the In-Phase/Quadrature-Phase (IQ) architecture to construct the modulation and demodulation processes of signal by utilizing a signal shaper scheme called Gaussian Frequency-Shift Keying (GFSK), in the short-rang communication it features strong anti-interference performance. Regarding with the OpenCL, it's one of High-Level Synthesis (HLS) methodsfor FPGAs design. It not only features high productive, but also can realize high operational efficiency for FPGA by using parallel programming architecture. Moreover, here invokes a remote platform called Intel DevCloud to control the FPGA for verifying the program, it would make the design more convenient and economic
XFVHDL4: A hardware synthesis tool for fuzzy systems
This paper presents a design technique that allows the automatic synthesis of fuzzy inference systems and accelerates the exploration of the design space of these systems. It is based on generic VHDL code generation which can be implemented on a programmable device (FPGA) or an application specific integrated circuit (ASIC). The set of CAD tools supporting this technique includes a specific environment for designing fuzzy systems, in combination with commercial VHDL simulation and synthesis tools. As demonstrated by the analyzed design examples, the described development strategy speeds up the stages of description, synthesis, and functional verification of fuzzy inference systems.Comunidad Europea FP7-IST-248858Ministerio de Ciencia e Innovación TEC2008-04920Junta de Andalucía P08-TIC-0367
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