Watermarking and Cryptography Based Image Authentication on Reconfigurable Platform

Now-a-days, multimedia based applications have been developed rapidly. Digital information is easy to process but it allows illegal users to access the data. For protecting the data from this illegal use, Digital Rights Management (DRM) can be used. DRM allows secure exchange of digital data over internet or other electronic media. In this paper, FPGA based implementation of DWT alongwith Advanced Encryption Standard (AES) based watermarking is discussed. With this approach, improved security can be achieved. The complete system is designed using HDL and simulated using Questasim and MATLAB Simulink model. The synthesis result shows that this implementation occupies only 2117 slices and maximum frequency reported for this design is 228.064 MHz

Hardware Implementation of a Secured Digital Camera with Built In Watermarking and Encryption Facility

The objective is to design an efficient hardware implementation of a secure digital camera for real time digital rights management (DRM) in embedded systems incorporating watermarking and encryption. This emerging field addresses issues related to the ownership and intellectual property rights of digital content. A novel invisible watermarking algorithm is proposed which uses median of each image block to calculate the embedding factor. The performance of the proposed algorithm is compared with the earlier proposed permutation and CRT based algorithms. It is seen that the watermark is successfully embedded invisibly without distorting the image and it is more robust to common image processing techniques like JPEG compression, filtering, tampering. The robustness is measured by the different quality assessment metrics- Peak Signal to Noise Ratio (PSNR), Normalized Correlation (NC), and Tampering Assessment Function (TAF). It is simpler to implement in hardware because of its computational simplicity. Advanced Encryption Standard (AES) is applied after quantization for increased security. The corresponding hardware architectures for invisible watermarking and AES encryption are presented and synthesized for Field Programmable Gate Array(FPGA).The soft cores in the form of Hardware Description Language(HDL) are available as intellectual property cores and can be integrated with any multimedia based electronic appliance which are basically embedded systems built using System On Chip (SoC) technology

VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application

This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of the biometric process in hardware like digital camera or scanners etc. To address such issues, a novel approach and its architecture in the framework of a digital camera, conceptualized as an SDC is presented. The SDC inserts biometric data into passport image with the aid of watermarking and encryption processes. The VLSI (very large scale integration) architecture of the functional units of the SDC such as watermarking and encryption unit is presented. The result of the hardware implementation of Rijndael advanced encryption standard (AES) and a discrete cosine transform (DCT) based visible and invisible watermarking algorithm is presented. The prototype chip can carry out simultaneous encryption and watermarking, which to our knowledge is the first of its kind. The encryption unit has a throughput of 500 Mbit/s and the visible and invisible watermarking unit has a max frequency of 96.31 MHz and 256 MHz respectively

Hardware and Software Codesign of a JPEG2000 Watermarking Encoder

Analog technology has been around for a long time. The use of analog technology is necessary since we live in an analog world. However, the transmission and storage of analog technology is more complicated and in many cases less efficient than digital technology. Digital technology, on the other hand, provides fast means to be transmitted and stored. Digital technology continues to grow and it is more widely used than ever before. However, with the advent of new technology that can reproduce digital documents or images with unprecedented accuracy, it poses a risk to the intellectual rights of many artists and also on personal security. One way to protect intellectual rights of digital works is by embedding watermarks in them. The watermarks can be visible or invisible depending on the application and the final objective of the intellectual work. This thesis deals with watermarking images in the discrete wavelet transform domain. The watermarking process was done using the JPEG2000 compression standard as a platform. The hardware implementation was achieved using the ALTERA DSP Builder and SIMULINK software to program the DE2 ALTERA FPGA board. The JPEG2000 color transform and the wavelet transformation blocks were implemented using the hardware-in-the-loop (HIL) configuration

FPGA Prototyping of a Watermarking Algorithm for MPEG-4

In the immediate future, multimedia product distribution through the Internet will become main stream. However, it can also have the side effect of unauthorized duplication and distribution of multimedia products. That effect could be a critical challenge to the legal ownership of copyright and intellectual property. Many schemes have been proposed to address these issues; one is digital watermarking which is appropriate for image and video copyright protection. Videos distributed via the Internet must be processed by compression for low bit rate, due to bandwidth limitations. The most widely adapted video compression standard is MPEG-4. Discrete cosine transform (DCT) domain watermarking is a secure algorithm which could survive video compression procedures and, most importantly, attacks attempting to remove the watermark, with a visibly degraded video quality result after the watermark attacks. For a commercial broadcasting video system, real-time response is always required. For this reason, an FPGA hardware implementation is studied in this work. This thesis deals with video compression, watermarking algorithms and their hardware implementation with FPGAs. A prototyping VLSI architecture will implement video compression and watermarking algorithms with the FPGA. The prototype is evaluated with video and watermarking quality metrics. Finally, it is seen that the video qualities of the watermarking at the uncompressed vs. the compressed domain are only 1dB of PSNR lower. However, the cost of compressed domain watermarking is the complexity of drift compensation for canceling the drifting effect

VLSI Watermark Implementations and Applications

This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common attacks and testing benchmarks are also briefly mentioned. It is shown that WM design must take the intended application into account. The difference between software and hardware implementations is explained through the introduction of a general scheme of a WM system and two examples from previous works. A versatile methodology to aid in a reliable and modular design process is suggested. Relating to mixed-signal VLSI design and testing, the proposed methodology allows an efficient development of a CMOS image sensor with WM capabilities

Digital image watermarking based on FPGA and spintronic logic and study of some aspects of spintronic logic based circuits.

The growth of high speed computer networks and that of Internet, in particular has explored means of new business , scientific , entertainment and social opportunities .Digital media offer several advantages over analog media like high quality ,easy editing ,high fidelity copying . There are enormous chances of duplicating and distribution of digital information which has led to the need for effective copyright protection tools . DIGITAL WATERMARKING is a kind of protection tool in which a data is hidden in an image ,audio file or video file .Watermarking is either “visible” or ”invisible” . Albeit visible or invisible are visual terms watermarking is not limited to images , it can also be used to protect other types of multimedia object . This project work is on Spatial Domain Image Watermarking using FPGA and Spintronic logic and applications of single spin logic where the spin of electron is used in addition to its charge .For the application of spintronics MAGNETIC TUNNEL JUNCTIONS (MTJ) are used as a spintronic device and different logic and ALU operations are performed and are compared with the conventional electronic devices based operation . The spintronic devices have lots of advantages over the conventional devices like they are non-volatile ,they consume less power ,timing and area