Thermal and thermo-mechanical performance of voided lead-free solder thermal interface materials for chip-scale packaged power device

The need to maximise thermal performance of electronic devices coupled with the continuing trends on miniaturization of electronic packages require innovative package designs for power devices and modules such as Electronic Control Unit (ECU). Chip scale packaging (CSP) technology offer promising solution for packaging power electronics. This is as a result of the technology’s relatively improved thermal performance and inherent size advantage. In CSP technology, heat removal from the device could be enhanced through the backside of the chip. Heat dissipating units such as heat spreader and/or heat sink can be attached to the backside (reverse side) of the heat generating silicon die (via TIM) in an effort to improve the surface area available for heat dissipation. TIMs are used to mechanically couple the heat generating chip to a heat sinking device and more crucially to enhance thermal transfer across the interface. Extensive review shows that solder thermal interface materials (STIMs) apparently offer better thermal performance than comparable state-of-the-art commercial polymer-based TIMs and thus a preferable choice in packaging power devices. Nonetheless, voiding remains a major reliability concern of STIMs. This is coupled with the fact that solder joints are generally prone to fatigue failures under thermal cyclic loading. Unfortunately, the occurrence of solder voids is almost unavoidable during manufacturing process and is even predominant in lead (Pb)-free solder joints. The impacts of these voids on the thermal and mechanical performance of solder joints are not clearly understood and scarcely available in literature especially with regards to STIMs (large area solder joints). Hence, this work aims to investigate STIM and the influence of voids on the thermo-mechanical and thermal performance of STIM. As previous results suggest that factors such as the location, configuration (spatial arrangement) and size of voids play vital roles on the exact effect of voids, extensive three dimensional (3D) finite element modelling is employed to elucidate the precise effect of these void features on a Pb-free STIM selected after thermo-mechanical fatigue test of standard Pb-free solder alloys. Finite element analysis (FEA) results show that solder voids configuration, size and location are all vital parameters in evaluating the mechanical and thermal impacts of voids. Depending on the location, configuration and size of voids; solder voids can either influence the initiation or propagation of damage in the STIM layer or the location of hot spot on the heat generating chip. Experimental techniques are further employed to compare and correlate levels of voiding and shear strength for representative Pb-free solders. Experimental results also suggest that void size, location and configuration may have an influence on the mechanical durability of solder joints. The findings of this research work would be of interest to electronic packaging engineers especially in the automotive sector and have been disseminated through publications in peer reviewed journals and presentations in international conferences

Interconnect Aging—Physics to Software

Device reliability or lifetime is often non-negotiable and crucial for sensitive applications such as medical devices, autonomous vehicles and space crafts. Inevitable technology advancement (e.g. miniaturization) has added unwelcome complications and unpredictability to the aging problem. Reliability of VLSI chips is jeopardized by mass transport in metallic interconnects. Material migration is caused by electrical, mechanical and thermal phenomena, and, therefore, is a complicated process. While all aspects of material migration have been studied, a comprehensive investigation that can explain and include all those phenomena simultaneously remains unsolved. Inaccuracies in modeling and predicting aging processes in wires cause that chipmakers often overdesign interconnects. This is an undesirable and expensive approach in terms of time and cost. In modern technologies, the predicted lifetime, aging, and failure mechanisms in interconnect very often do not match the observed behaviors. Unrealistic models used in CAD tools are the main culprit of such incompatibilities. In general, two situations may occur: (1) in some cases, the models may wrongly scrutinize reliability in unfailing parts and consequently impose unnecessary design tightening and (2) in some other cases, the models may underestimate serious reliability problems causing unpredicted behaviors or catastrophic failures to occur. The existing models for reliability evaluation are usually pessimistic in case of interconnect voiding and optimistic when extrusions occur. Time-consuming and not converging reliability assessments, as well as undesired chip behaviors, are the common expensive outcome of such models.We revisit the underlying physics of aging processes in dual-damascene copper lines. We demonstrate, that the simplistic modeling is the cause of the incompatibility of the existing models. We study all three main aging processes: electromigration, thermo-migration, and stress migration and offer several comprehensive yet compact models for realistic assessment of interconnect aging. These models explain many observations that have been inexplicable for decades. Ultimately, a computer-aided design tool, RAIN, is developed based on the proposed models and is capable of assessing the reliability of industry standard complex multi-layer, multi-segment interconnect networks. This tool can be readily integrated into other verification signoffs phases such as performance, timing, and power analyses. RAIN takes as inputs: (1) interconnect design, (2) technology specifications, (3) initial stress and temperature, (4) IR drop and lifetime requirements. It analyzes and assesses reliability and delivery requirements of all nets, and provides a report on voltage limitations, thermal violations and expected lifetime. It is validated on a wide spectrum of experimental results performed on various industry benchmarks

Fundamental Studies of Tin Whiskering in Microelectronics Finishes

Fundamental Studies of Tin Whiskering in Microelectronics Finishes Abstract Common electronics materials, such as tin, copper, steel, and brass, are ambient reactive under common use conditions, and as such are prone to corrosion. During the early 1940s, reports of failures due to electrical shorting of components caused by `whisker' (i.e., filamentary surface protrusion) growth on many surface types - including the aforementioned metals - began to emerge. Lead alloying of tin (3-10% by weight, typically in the eutectic proportion) eliminated whiskering risk for decades, until the July 2006 adoption of the Restriction of Hazardous Substances (RoHS) directive was issued by the European Union. This directive, which has since been adopted by California and parts of China, severely restricted the use of lead (<1000 ppm) in all electrical and electronics equipment being placed on the EU market, imposing the need for developing reliable new "lead-free" alternatives to SnPb. In spite of the abundance of modern-day anecdotes chronicling whisker-related failures in satellites, nuclear power stations, missiles, pacemakers, and spacecraft navigation equipment, pure tin finishes are still increasingly being employed today, and the root cause(s) of tin whiskering remains elusive. This work describes a series of structured experiments exploring the fundamental relationships between the incidence of tin whiskering (as dependent variable) and numerous independent variables. These variables included deposition method (electroplating, electroless plating, template-based electrochemical synthesis, and various physical vapor deposition techniques, including resistive evaporation, electron beam evaporation, and sputtering), the inclusion of microparticles and organic contamination, the effects of sample geometry, and nanostructuring. Key findings pertain to correlations between sample geometry and whisker propensity, and also to the stress evolution across a series of 4"-diameter silicon wafers of varying thicknesses with respect to the degree of post-metallization whiskering. Regarding sample geometry, it was found that smaller, thinner substrates displayed a more rapid onset of whiskering immediately following metallization. Changes in wafer-level stress were not found to correlate with whiskering morphology (number, density, length) after 6 weeks of aging. This result points either to the irrelevance of macrostress in the substrate/film composite, or to a difference in whiskering mechanism for rigid substrates (whose stress gradient over time is significant) when compared with thinner, flexible susbtrates (whose stress is less variable with time). Organic contamination was found to have no appreciable effect when explicitly introduced. Furthermore, electron-beam evaporated films whiskered more readily than films deposited via electroplating from baths containing organic "brighteners." Beyond such findings, novel in themselves, our work is also unique in that we emphasize the "clean" deposition of tin (with chromium adhesion layers and copper underlayers) by vacuum-based physical vapor deposition, to circumvent the question of contamination entirely. By employing silicon substrates exclusively, we have distinguished ourselves from other works (which, for example, use copper coupons fabricated from rolled shim stock) because we have better sample-to-sample consistency in terms of material properties, machinability, and orientation

Finite Element Modeling of the Effect of Reflow Porosity on the Mechanical Behavior of Pb-free Solder Joints

abstract: Pb-free solders are used as interconnects in various levels of micro-electronic packaging. Reliability of these interconnects is very critical for the performance of the package. One of the main factors affecting the reliability of solder joints is the presence of porosity which is introduced during processing of the joints. In this thesis, the effect of such porosity on the deformation behavior and eventual failure of the joints is studied using Finite Element (FE) modeling technique. A 3D model obtained by reconstruction of x-ray tomographic image data is used as input for FE analysis to simulate shear deformation and eventual failure of the joint using ductile damage model. The modeling was done in ABAQUS (v 6.10). The FE model predictions are validated with experimental results by comparing the deformation of the pores and the crack path as predicted by the model with the experimentally observed deformation and failure pattern. To understand the influence of size, shape, and distribution of pores on the mechanical behavior of the joint four different solder joints with varying degrees of porosity are modeled using the validated FE model. The validation technique mentioned above enables comparison of the simulated and actual deformation only. A more robust way of validating the FE model would be to compare the strain distribution in the joint as predicted by the model and as observed experimentally. In this study, to enable visualization of the experimental strain for the 3D microstructure obtained from tomography, a three dimensional digital image correlation (3D DIC) code has been implemented in MATLAB (MathWorks Inc). This developed 3D DIC code can be used as another tool to verify the numerical model predictions. The capability of the developed code in measuring local displacement and strain is demonstrated by considering a test case.Dissertation/ThesisM.S. Mechanical Engineering 201

3-D time-depending simulation of void formation in metallization structures

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Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects

textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic

Physics-Based Electromigration Modeling and Analysis and Optimization

Long-term reliability is a major concern in modern VLSI design. Literature has shown that reliability gets worse as technology advances. It is expected that the future VLSI systems would have shorter reliability-induced lifetime comparing with previous generations. Being one of the most serious reliability effects, electromigration (EM) is a physical phenomenon of the migration of metal atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change or open circuit and result in functional failure of the circuit. Power-ground networks are the most vulnerable part to EM effect among all the interconnect wires since the current flow on this part is the largest on the chip. With new generation oftechnology node and aggressive design strategies, more accurate and efficient EM models are required. However, traditional EM approaches are very conservative and cannot meet current aggressive design strategies. Besides circuit level, EM also need to be thoroughly studied in system level due to limited power and temperature budgets among cores on chip. This research focuses on developing physical level EM model for VLSI circuits and system level EM optimization for multi-core systems in order to overcome the aforementioned problems. Specifically, for physical level, we develop two EM immortality check methods and a power grid EM check method. Firstly, a voltage based EM immortality analysis has been developed. Immortality condition in nucleation phase can be determined fast and accurately for multi-segment interconnect wires. Secondly, a saturation volume based incubation phase immortality check method has been proposed. This method can further reduce the redundancy in VLSI circuit design by immortality check in multiphase. Furthermore, both immortality check methods are integrated into a new power grid EM check methodology (EMspice) as filter for EM analysis. These filters can accelerate the simulation by filtering out immortal trees so that we only need to do simulation on fewer trees that are mortal. Coupled EM simulation considering both hydrostatic stress and electronic current/voltage in the power grid network will be applied to these mortal trees. This tool can work seamlessly with commercial synthesis flow. Besides physical level reliability models, system level reliability optimization is also discussed in this research. A deep reinforcement learning based EM optimization has been proposed for multi-core system. Both long term reliability effect (hard error) and transient soft error are considered. Energy can be optimized with all the reliability and other constraints fast and accurately compared to existing reliability management techniques. Last but not least, a scheduling based reliability optimization method for multi-core systems has been proposed. NBTI, HCI and EM are considered jointly. Lifetime of the system can be improved significantly compared to traditional methods which mainly focus on utilization

Properties and behaviour of Pb-free solders in flip-chip scale solder interconnections

Due to pending legislations and market pressure, lead-free solders will replace Sn–Pb solders in 2006. Among the lead-free solders being studied, eutectic Sn–Ag, Sn–Cu and Sn–Ag–Cu are promising candidates and Sn–3.8Ag–0.7Cu could be the most appropriate replacement due to its overall balance of properties. In order to garner more understanding of lead-free solders and their application in flip-chip scale packages, the properties of lead free solders, including the wettability, intermetallic compound (IMC) growth and distribution, mechanical properties, reliability and corrosion resistance, were studied and are presented in this thesis. [Continues.

Modeling the SAC microstructure evolution under thermal, thermomechanical and electrical constraints

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