Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764

Arbitrary Hardware/Software Trade Offs

This paper discusses a novel transformation-based design methodology and its use in the design of complex programmable VLSI systems. During the life-cycle of a complex system, the optimal trade-off between partially implementing in hardware or software is changing. This is due to varying system requirements (short time-to-market, low-cost, low-power, etc.) and improving the device technology. The proposed methodology allows such redesigns to be made using different hardware-software trade-offs, in a guaranteed correct wa

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving high performance and extending product functionality and lifetime via the addition of new features that operate at hardware speed. However, designing a changing hardware system is both challenging and time-consuming. FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Our tool-chain supports both coarse- and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources. We target three applications from different domains. We explore the way each application benefits from reconfiguration, and then we asses them and the FASTER tools, in terms of performance, area consumption and accuracy of analysis

Design and application of reconfigurable circuits and systems

Open Acces

High-level variable selection for partial-scan implementation

In this paper, we propose a high-level variable se-lection for partial-scan approach to improve the testa-bility of digital systems. The testability of a design is evaluated at the high level based on previously proposed controllability and observability measures. A testabil-ity grading technique is utilized to measure the rela-tive testability improvement in a design as the result of making a subset of the variables fully controllable and observable. The variables that cause the greatest testa-bility improvement are selected, and the selection pro-cess is performed incrementally until no further testa-bility improvement can be achieved. Then the registers that correspond to the selected variables are placed in the scan-chain for partial-scan implementation. The experimental results shows that the variable selection approach produces partial-scan implementations that can achieve high fault coverage, while the logic over-heads are fairly low.