5 research outputs found

    Real time fault injection using enhanced OCD - a performance analysis

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    Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead

    A Remote Verification Framework to Assess the Robustness of Circuits to Soft Faults

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    The growing number of circuits implemented in Field Programmable Gate Arrays (FPGAs) and the increased susceptibility, due to higher integration levels, of these devices to soft faults caused by radiation at ground level is leading the scientific and technical community to the study of new fault tolerant designs and solutions, and how they can be verified and validated. Using fault injection techniques and enhanced debug tools to inject faults in a circuit and observing its behaviour in the presence of such faults, respectively, is a proven solution for the previous verification and validation problem. This paper presents the underlying concepts for a remote verification framework to assess the robustness of circuits to soft faults. It comprises a verification platform and a set of verification services that can be used in a remote or local fashions.info:eu-repo/semantics/publishedVersio

    UML-Based Modeling of Robustness Testing

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    Abstract-The aim of robustness testing is to characterize the behavior of a system in the presence of erroneous or stressful input conditions. It is a well-established approach in the dependability community, which has a long tradition of testing based on fault injection. However, a recurring problem is the insufficient documentation of experiments, which may prevent their replication. Our work investigates whether UMLbased documentation could be used. It proposes an extension of the UML Testing Profile that accounts for the specificities of robustness testing experiments. The extension also reuses some elements of the QoSFT profile targeting measurements. Its ability to model realistic experiments is demonstrated on a case study from dependability research

    Real-time fault injection using enhanced on-chip debug infrastructures

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    The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead
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