5,766 research outputs found
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
Analog Circuits in Ultra-Deep-Submicron CMOS
Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena
Investigation of FACTS devices to improve power quality in distribution networks
Flexible AC transmission system (FACTS) technologies are power electronic solutions
that improve power transmission through enhanced power transfer volume and stability,
and resolve quality and reliability issues in distribution networks carrying sensitive
equipment and non-linear loads. The use of FACTS in distribution systems is still in
its infancy. Voltages and power ratings in distribution networks are at a level where
realistic FACTS devices can be deployed. Efficient power converters and therefore loss
minimisation are crucial prerequisites for deployment of FACTS devices.
This thesis investigates high power semiconductor device losses in detail. Analytical
closed form equations are developed for conduction loss in power devices as a function
of device ratings and operating conditions. These formulae have been shown to predict
losses very accurately, in line with manufacturer data. The developed formulae enable
circuit designers to quickly estimate circuit losses and determine the sensitivity of those
losses to device voltage and current ratings, and thus select the optimal semiconductor
device for a specific application.
It is shown that in the case of majority carrier devices (such as power MOSFETs), the
conduction power loss (at rated current) increases linearly in relation to the varying rated
current (at constant blocking voltage), but is a square root of the variable blocking voltage
when rated current is fixed. For minority carrier devices (such as a pin diode or IGBT),
a similar relationship is observed for varying current, however where the blocking voltage
is altered, power losses are derived as a square root with an offset (from the origin).
Finally, this thesis conducts a power loss-oriented evaluation of cascade type multilevel
converters suited to reactive power compensation in 11kV and 33kV systems. The cascade
cell converter is constructed from a series arrangement of cell modules. Two prospective
structures of cascade type converters were compared as a case study: the traditional type
which uses equal-sized cells in its chain, and a second with a ternary relationship between
its dc-link voltages. Modelling (at 81 and 27 levels) was carried out under steady state
conditions, with simplified models based on the switching function and using standard
circuit simulators. A detailed survey of non punch through (NPT) and punch through
(PT) IGBTs was completed for the purpose of designing the two cascaded converters.
Results show that conduction losses are dominant in both types of converters in NPT
and PT IGBTs for 11kV and 33kV systems. The equal-sized converter is only likely to
be useful in one case (27-levels in the 33kV system). The ternary-sequence converter
produces lower losses in all other cases, and this is especially noticeable for the 81-level
converter operating in an 11kV network
Transient electrothermal simulation of power semiconductor devices
In this paper, a new thermal model based on the Fourier series solution of heat conduction equation has been introduced in detail. 1-D and 2-D Fourier series thermal models have been programmed in MATLAB/Simulink. Compared with the traditional finite-difference thermal model and equivalent RC thermal network, the new thermal model can provide high simulation speed with high accuracy, which has been proved to be more favorable in dynamic thermal characterization on power semiconductor switches. The complete electrothermal simulation models of insulated gate bipolar transistor (IGBT) and power diodes under inductive load switching condition have been successfully implemented in MATLAB/Simulink. The experimental results on IGBT and power diodes with clamped inductive load switching tests have verified the new electrothermal simulation model. The advantage of Fourier series thermal model over widely used equivalent RC thermal network in dynamic thermal characterization has also been validated by the measured junction temperature
Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS
In questo lavoro si presenta una metodologia di
progettazione elettronica a livello di sistema,
affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su
campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di
equazioni atti a selezionare le configurazione di
interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre,
il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso
Integrated chaos generators
This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110
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