A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V

Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages

A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability. The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling. A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Green’s Function (GF) approach can be seen as a breakthrough methodology. One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits. This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Modelling and Simulation of Silicon Nanowire-Based Electron Devices for Computation and Sensing

Silicon Nanowires (SiNWs) are considered the fundamental component blocks of future nanoelectronics. Many interesting properties have gained them such a prominent position in the investigation in recent decades. Large surface-to-volume ratio, bio-compatibility, band-gap tuning are among the most appealing features of SiNWs. More importantly, in the ongoing process of dimension miniaturization, SiNWs compatibility with the existing and reliable silicon technology stands as a fundamental advantage. Consequently, the employment of SiNWs spred in several application fields: from computational logic where SiNWs are used to realize transistors, to bio-chemical sensing and nanophotonic applications. In this thesis work we concentrate our attention on the employment of SiNWs in computational logic and bio-chemical sensing. In particular, we aim at giving a contribution in the modelling and simulation of SiNW-based electron devices. Given the current intense investigation of new devices, the modelling of their electrical behaviour is strongly required. On one side, modelling procedures could give an insight on the physical phenomena of transport in nanometer scale systems where quantum effects are dominant. On the other side, the availability of compact models for actual devices can be of undeniable help in the future design process. This work is divided into two parts. After a brief introduction on Silicon Nanowires, the main fabrication techniques and their properties, the first part is dedicated to the modelling of Multiple-Independent Gate Transistors, a new generation of devices arisen from the composition of Gate-All-Around Transistors, finFETs and Double-Gate Transistors. Interesting applications resulting from their employment are Vertically-stacked Silicon Nanowire FETs, known to have an ambipolar behaviour, and Silicon Nanowire Arrays. We will present a compact numerical model for composite Multiple-Independent Gate Transistors which allows to compute current and voltages in complex structures. Validation of the model through simulation proves the accuracy and the computational efficiency of the resulting model. The second part of the thesis work is instead devoted to Silicon Nanowires for bio-chemical sensing. In this respect, major attention is given to Porous Silicon (PS), a non-crystalline material which demonstrated peculiar features apt for sensing. Given its not regular microscopic morphology made of a complex network of crystalline and non-crystalline regions, PS has large surface-to-volume ratio and a relevant chemical reactivity at room temperature. In this work we start from the fabrication of PS nanowires at Istituto Nazionale di Ricerca Metrologica in Torino (I.N.Ri.M.) to devise two main models for PSNWs which can be used to understand the effects of porosity on electron transport in these structures. The two modelling procedures have different validity regimes and efficiently take into account quantum effects. Their description and results are presented. The last part of the thesis is devoted to the impact of surface interaction of molecular compounds and dielectric materials on the transport properties of SiNWs. Knowing how molecules interact with silicon atoms and how the conductance of the wire is affected is indeed the core of SiNWs used for bio-chemical sensing. In order to study the phenomena involved, we performed ab-initio simulations of silicon surface interacting with SO2 and NO2 via the SIESTA package, implementing DFT code. The calculations were performed at Institut de Ciencia De Materials de Barcelona (ICMAB-CSIC) using their computational resources. The results of this simulation step are then exploited to perform simulation of systems made of an enormous quantity of atoms. Due to their large dimensions, atomistic simulations are not affordable and other approaches are necessary. Consequently, calculations with physics-based softwares on a larger spatial scale were adopted. The description of the obtained results occupies the last part of the work together with the discussion of the main theoretical insight gained with the conducted study

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Intelligent Circuits and Systems

ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society.　 This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering

Efficient algorithms for fundamental statistical timing analysis problems in delay test applications of VLSI circuits

Tremendous advances in semiconductor process technology are creating new challenges for the delay test of today’s digital VLSI circuits. The complexity of state-of-the-art manufacturing processes does not only lead to greater process variability, it also makes today's integrated circuits more prone to defects such as resistive shorts and opens. As a consequence, some of the manufactured circuits do not meet the timing requirements set by the design specification. These circuits must be identified by delay testing and sorted out to ensure the quality of shipped products. Due to the increasing process variability, key transistor and interconnect parameters must be modelled as random variables. These random variables capture the uncertainty caused by process variability, but also the impact of modelling errors and variations in the operating conditions of the circuits, such as the temperature or the supply voltage. The important consequence for delay testing is that a particular delay test detects a delay fault of fixed size in only a subset of all manufactured circuits, which inevitably leads to the shipment of defective products. Despite the fact that this problem is well understood, today's delay test generation methods are unable to consider the distortion of the delay test results, caused by process variability. To analyse and predict the effectiveness of delay tests in a population of circuits which are functionally identical but have varying timing properties, statistical timing analysis is necessary. Although the large runtime of statistical timing analysis is a well known problem, little progress has been made in the development of efficient statistical timing analysis algorithms for the variability-aware delay test generation and delay fault simulation. This dissertation proposes novel and efficient statistical timing analysis algorithms for the variability-aware delay test generation and delay fault simulation in presence of large delay variations. For the detection of path delay faults, a novel probabilistic sensitization analysis is presented which analyses the impact of process variations on the sensitization of the target paths. Furthermore, an efficient method for approximating the probability of detecting small delay faults is presented. Beyond that, efficient statistical SUM and MAX-operations are proposed, which provide the fundamental basis of block-based statistical timing analysis. The experiment results demonstrate the high efficiency of the proposed algorithms

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within