Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture

科研費報告書収録論文(課題番号:17300009/研究代表者:亀山充隆/システムインテグレーション理論に基づく高安全知能自動車用VLSIの最適設計

Adaptive code division multiple access protocol for wireless network-on-chip architectures

Massive levels of integration following Moore\u27s Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol outperformed the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. Significant gains were observed in packet energy dissipation and bandwidth even with scaling the system to higher number of cores. Non-uniform traffic simulations showed that the proposed CDMA-WiNoC was consistent in bandwidth across all traffic patterns. It is also shown that the CDMA based MAC scheme does not introduce additional reliability concerns in data transfer over the on-chip wireless interconnects

Design Trade-offs for reliable On-Chip Wireless Interconnects in NoC Platforms

The massive levels of integration following Moore\u27s Law making modern multi-core chips prevail in various domains ranging from scientific applications to bioinformatics applications for consumer electronics. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. An efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. A token-passing protocol proposed to grant access of the wireless channel to competing transmitters. This limits the number of simultaneous users of the communication channel to one although multiple wireless hubs are deployed over the chip. In principle, a Frequency Division Multiple Access (FDMA) based medium access scheme would improve the utilization of the wireless resources. However, this requires design of multiple very precise, high frequency transceivers in non-overlapping frequency channels. Therefore, the scalability of this approach is limited by the state-of-the-art in transceiver design. The Code Division Multiple Access (CDMA) enables multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. The CDMA protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. The CDMA based MAC protocol outperforms the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. However, the reliability of CDMA based wireless NoC\u27s is limited, as the probability of error is eminent due to synchronization delays at the receiver. The thesis proposes the use of an advanced filter which improves the performance and also reduces the error due to synchronization delays. This thesis also proposes investigation of various channel modulation schemes on token passing wireless NoC\u27s to examine the performance and reliability of the system. The trade-off between performance and energy are established for the various conditions. The results are obtained using a modified cycle accurate simulator

Esquemas de pré-codificação IA com IB-DFE para sistemas MC-CDMA

Mestrado em Engenharia Eletrónica e TelecomunicaçõesTo achieve high bit rates, needed to meet the quality of service requirements of future multimedia applications, multi-carrier code division multiple access (MC-CDMA) has been considered as a candidate air-interface. Interference alignment (IA) is a promising technique that allows high capacity gains in interfering channels. On the other hand, iterative block decision feedback equalization (IB-DFE) based receivers can efficiently exploit the inherent space-frequency diversity of the MIMO MC-CDMA systems. In this thesis we proposed an IA precoding at the transmitter with IB-DFE based processing at the receiver for MC-CDMA systems. The IA precoding is applied at chip level instead of the data symbols level, as in the conventional IA based systems. The receiver is designed in two steps: first the equalizers based on zero forcing (ZF) or minimum mean square error (MMSE) are used to remove the aligned users´ interference. Then and after a whitening noise process, an IB-DFE based equalizer is designed to remove both the residual inter-user aligned and inter-carrier interferences. The results have shown that the obtained performance is very close to the one obtained by the optimal matched filter, with few iterations at the receiver side.Para atingir maiores ritmos de transmissão, as futures aplicações multimédia necessitam de atingir a qualidade de serviço necessária. Para isso, o multi-carrier code division multiple access (MC-CDMA) tem sido apontado como um forte candidato para interface ar dos futuros sistemas celulares. O Interference Alignment (IA) ou alinhamento de interferência é uma técnica promissora que permite ter altos ganhos de capacidade em canais com interferência. Por outro lado, temos receptores baseados no conceito iterative block decision feedback equalization(IB-DFE) que conseguem tirar partido, de uma forma eficiente, da inerente diversidade espaço-frequência dos sistemas MIMO MC-CDMA. Nesta dissertação é implementada uma pré-codificação baseada no conceito de IA considerando três transmissores (ou estações base) juntamente, com um processamento IB-DFE no receptor para sistemas MC-CDMA.A pré-codificação é aplicada ao nível de chip em vez de ser aplicado ao nível dos dados. O receptor é projectado em dois passos: em primeiro lugar equalizadores baseados em ZF ou em MMSE são utilizados para remover a interferência alinhada dos restantes utilizadores. De seguida, e após aplicar um processo de branqueamento do ruído ao sinal à saída do primeiro equalizador, um segundo equalizador baseado em IB-DFE é projectado para remover a interferência inter-utilizador residual e também a interferência residual entre portadoras. Os resultados obtidos mostraram-se satisfatórios na remoção da interferência obtendo-se um desempenho muito próximo do obtido considerando um filtro adaptado

An efficient asynchronous spatial division multiplexing router for network-on-chip on the hardware platform

The quasi-delay-insensitive (QDI) based asynchronous network-on-chip (ANoC) has several advantages over clock-based synchronous network-on-chips (NoCs). The asynchronous router uses a virtual channel (VC) as a primary flow-control mechanism however, the spatial division multiplexing (SDM) based mechanism performs better over input traffics over VC. This manuscript uses an asynchronous spatial division multiplexing (ASDM) based router for NoC architecture on a field-programmable gate array (FPGA) platform. The ASDM router is configurable to different bandwidths and VCs. The ASDM router mainly contains input-output (I/O) buffers, a switching allocator, and a crossbar unit. The 4-phase 1-of-4 dual-rail protocol is used to construct the I/O buffers. The performance of the ASDM router is analyzed in terms of lower urinary tract symptoms (LUTs) (chip area), delay, latency, and throughput parameters. The work is implemented using Verilog-HDL with Xilinx ISE 14.7 on artix-7 FPGA. The ASDM router achieves % chip area and obtains 0.8 ns of latency with a throughput of 800 Mfps. The proposed router is compared with existing asynchronous approaches with improved latency and throughput metrics

Low-overhead hard real-time aware interconnect network router

The increasing complexity of embedded systems is accelerating the use of multicore processors in these systems. This trend gives rise to new problems such as the sharing of on-chip network resources among hard real-time and normal best effort data traffic. We propose a network-on-chip router that provides predictable and deterministic communication latency for hard real-time data traffic while maintaining high concurrency and throughput for best-effort/general-purpose traffic with minimal hardware overhead. The proposed router requires less area than non-interfering networks, and provides better Quality of Service (QoS) in terms of predictability and determinism to hard real-time traffic than priority-based routers. We present a deadlock-free algorithm for decoupled routing of the two types of traffic. We compare the area and power estimates of three different router architectures with various QoS schemes using the IBM 45-nm SOI CMOS technology cell library. Performance evaluations are done using three realistic benchmark applications: a hybrid electric vehicle application, a utility grid connected photovoltaic converter system, and a variable speed induction motor drive application

Near-Instantaneously Adaptive HSDPA-Style OFDM Versus MC-CDMA Transceivers for WIFI, WIMAX, and Next-Generation Cellular Systems

Burts-by-burst (BbB) adaptive high-speed downlink packet access (HSDPA) style multicarrier systems are reviewed, identifying their most critical design aspects. These systems exhibit numerous attractive features, rendering them eminently eligible for employment in next-generation wireless systems. It is argued that BbB-adaptive or symbol-by-symbol adaptive orthogonal frequency division multiplex (OFDM) modems counteract the near instantaneous channel quality variations and hence attain an increased throughput or robustness in comparison to their fixed-mode counterparts. Although they act quite differently, various diversity techniques, such as Rake receivers and space-time block coding (STBC) are also capable of mitigating the channel quality variations in their effort to reduce the bit error ratio (BER), provided that the individual antenna elements experience independent fading. By contrast, in the presence of correlated fading imposed by shadowing or time-variant multiuser interference, the benefits of space-time coding erode and it is unrealistic to expect that a fixed-mode space-time coded system remains capable of maintaining a near-constant BER

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

We propose an approach for computing the end-to-end delay bound of individual variable bit-rate flows in a FIFO multiplexer with aggregate scheduling under Weighted Round Robin (WRR) policy. To this end, we use network calculus to derive per-flow end-to-end equivalent service curves employed for computing Least Upper Delay Bounds (LUDBs) of individual flows. Since real time applications are going to meet guaranteed services with lower delay bounds, we optimize weights in WRR policy to minimize LUDBs while satisfying performance constraints. We formulate two constrained delay optimization problems, namely, Minimize-Delay and Multiobjective optimization. Multi-objective optimization has both total delay bounds and their variance as minimization objectives. The proposed optimizations are solved using a genetic algorithm. A Video Object Plane Decoder (VOPD) case study exhibits 15.4% reduction of total worst-case delays and 40.3% reduction on the variance of delays when compared with round robin policy. The optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces. We conclude that an appropriate weight allocation can be a valuable instrument for delay optimization in on-chip network designs