Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs

Trade-off between power and bandwidth consumption in a reconfigurable xhaul network architecture

The increasing number of wireless devices, the high required traffic bandwidth, and power consumption will lead to a revolution of mobile access networks, which is not a simple evolution of traditional ones. Cloud radio access network technologies are seen as promising solution in order to deal with the heavy requirements defined for 5G mobile networks. The introduction of the common public radio interface (CPRI) technology allows for a centralization in BaseBand unit (BBU) of some access functions with advantages in terms of power consumption saving when switching off algorithms are implemented. Unfortunately, the advantages of the CPRI technology are to be paid with an increase in required bandwidth to carry the traffic between the BBU and the radio remote unit (RRU), in which only the radio functions are implemented. For this reason, a tradeoff solution between power and bandwidth consumption is proposed and evaluated. The proposed solution consists of: 1) handling the traffic generated by the users through both RRU and traditional radio base stations (RBS) and 2) carrying the traffic generated by the RRU and RBS (CPRI and Ethernet flows) with a reconfigurable network. The proposed solution is investigated under the lognormal spatial traffic distribution assumption. After proposing resource dimensioning analytical models validated by simulation, we show how the sum of the bandwidth and power consumption may be minimized with the deployment of a given percentage of RRU. For instance we show how in 5G traffic scenarios this percentage can vary from 30% to 50% according to total traffic amount handled by a switching node of the reconfigurable network

Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code