Design of a band-pass filter in 0,18 μm CMOS for 2,4 GHz reader-less RFID transponder

Sustavi temeljeni na Radio Frequency Identification (RFID) sada su široko rasprostranjeni. Pojasno fazni filtri igraju važnu ulogu u funkcioniranju RFID transpondera. U ovom radu, pojasno fazni filtar s induktorom aktivnim samo s tranzistorom prikazan je za kompaktni RFID transponder bez čitača visokih performansi. Rezultat simulacije rasporeda otkriva da središnja frekvencija filtra može biti postavljena na frekvenciju od 2,42 GHz sa širinom pojasa od 38 MHz. Jezgra filtra zauzima površinu od 0,004 mm2 i gubi samo 1,3 mW kod napona napajanja od 1,5 V. Predloženi filtar dizajniran je pomoću CEDEC 0,18 μm CMOS tehnologije u Mentor Graphics okruženju.Radio Frequency Identification (RFID) based systems are ubiquitous nowadays. Band pass filters always play an important role in overall performance of an RFID transponder. In this paper, a band pass filter with a transistor only active inductor is presented for compact high performance reader-less RFID transponder. Post layout simulation result reveals that the centre frequency of the filter can be set to 2,42 GHz frequency with a bandwidth of 38 MHz. The filter core occupies an area of 0,004 mm2 and dissipates only 1,3 mW at 1,5 V supply voltage. CEDEC 0,18 μm CMOS technology in Mentor Graphics environment has been used for the design of the proposed filter

Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s. The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter- Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities. In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system

Developing a Model for Explaining Network Attributes and Relationships of Organised Crime Activities by Utilizing Network Science

The main objective of this research is to provide an innovative exploratory model for investigating substantive organised crime activities. The study articulates 30 critical independent variables related to organised crime, network science and a comprehensive exploratory approach which converts measurements of the variables into meaningful crime related inferences and conclusions. A case study was conducted to review initial feasibility of the selected variables, exploratory approach and model, and the results suggesting good effectiveness and useability