Supply Current Modeling and Analysis of Deep Sub-Micron Cmos Circuits

Continued technology scaling has introduced many new challenges in VLSI design. Instantaneous switching of the gates yields high current flow through them that causes large voltage drop at the supply lines. Such high instantaneous currents and voltage drop cause reliability and performance degradation. Reliability is an issue as high magnitude of current can cause electromigration, whereas, voltage drop can slow down the circuit performance. Therefore, designing power supply lines emphasizes the need of computing maximum current through them. However, the development of digital integrated circuits in short design cycle requires accurate and fast timing and power simulation. Unfortunately, simulators that employ device modeling methods, such as HSPICE are prohibitively slow for large designs. Therefore, methods which can produce good maximum current estimates in short times are critical. In this work a compact model has been developed for maximum current estimation that speeds up the computation by orders of magnitude over the commercial tools

Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input

In low power current mode signal processing circuits it is often necessary to use current mirrors to replicate and amplify/attenuate current signals and clamp the voltage of nodes with high parasitic capacitances so that the smallest currents do not introduce unacceptable delays. The use of tunable active-input current mirrors would meet both requirements. In conventional active-input current mirrors, stability compensation is required. Furthermore, once stabilized, the input current cannot be made arbitrarily small. In this paper we introduce two new active-input current mirrors that clamp their input node to a given voltage. One of them does not require compensation, while the other may under some circumstances. However, for both, the input current may take any value. The mirrors can operate with their transistors biased in strong inversion, weak inversion, or even as CMOS compatible lateral bipolar devices. If it is biased in weak inversion or as lateral bipolars, the current mirror gain can be tuned over a very wide range. According to the experimental measurements provided in this paper, the input current may spawn beyond nine decades and the current mirror gain can be tuned over 11 decades. As an application example, a sinusoidal gm-C-based VCO has been fabricated, whose oscillation frequency could be tuned for over seven decades, between 74 mHz and 1 MHz.Office of Naval Research (USA) N00014-95-1-040

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

A Millimeter-scale Single Charged Particle Dosimeter for Cancer Radiotherapy

This paper presents a millimeter-scale CMOS 64$\times$64 single charged particle radiation detector system for external beam cancer radiotherapy. A 1$\times$1 $\mu m^2$ diode measures energy deposition by a single charged particle in the depletion region, and the array design provides a large detection area of 512$\times$512 $\mu m^2$. Instead of sensing the voltage drop caused by radiation, the proposed system measures the pulse width, i.e., the time it takes for the voltage to return to its baseline. This obviates the need for using power-hungry and large analog-to-digital converters. A prototype ASIC is fabricated in TSMC 65 nm LP CMOS process and consumes the average static power of 0.535 mW under 1.2 V analog and digital power supply. The functionality of the whole system is successfully verified in a clinical 67.5 MeV proton beam setting. To our' knowledge, this is the first work to demonstrate single charged particle detection for implantable in-vivo dosimetry

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

A software controlled voltage tuning system using multi-purpose ring oscillators

This paper presents a novel software driven voltage tuning method that utilises multi-purpose Ring Oscillators (ROs) to provide process variation and environment sensitive energy reductions. The proposed technique enables voltage tuning based on the observed frequency of the ROs, taken as a representation of the device speed and used to estimate a safe minimum operating voltage at a given core frequency. A conservative linear relationship between RO frequency and silicon speed is used to approximate the critical path of the processor. Using a multi-purpose RO not specifically implemented for critical path characterisation is a unique approach to voltage tuning. The parameters governing the relationship between RO and silicon speed are obtained through the testing of a sample of processors from different wafer regions. These parameters can then be used on all devices of that model. The tuning method and software control framework is demonstrated on a sample of XMOS XS1-U8A-64 embedded microprocessors, yielding a dynamic power saving of up to 25% with no performance reduction and no negative impact on the real-time constraints of the embedded software running on the processor

Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits

Abstract We present two new algorithms for generating a small set of patterns for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. The rst algorithm is based on timed ATPG, while the second is a probability-based approach. Both algorithms can handle circuits with arbitrary but known delays and they produce a set of 2-vector tests. Experimental results demonstrating that the outcome of applying our algorithms is a small set of patterns producing a current that is a tight l o w er bound on the maximum instantaneous current are included