Verification of Identity and Syntax Check of Verilog and LEF Files

The Verilog and LEF files are units of the digital design flow [1][2]. They are being developed in different stages. Before the development of the LEF file, the Verilog file passes through numerous steps during which partial losses of information are possible. The identity check allows to make sure that during the flow the information has not been lost. The syntax accuracy of the Verilog and LEF files is checked as well. nbspnbspnbspnbspnbspnbspnbspnbspnbspnbspnbsp The scripting language Perl is selected for the program. The language is flexible to work with text files [3]. nbspnbspnbspnbspnbspnbspnbspnbspnbspnbspnbsp The method developed in the present paper is substantial as the application of integrated circuits today is actual in different scientific, technical and many other spheres which gradually finds wider application bringing about large demand

Complete-Range Activity-Based RTL Power Estimation

In recent years, power consumption has become a major concern in the electronic industry. Power reduction can be accelerated in the design cycle by fast and accurate power estimation tools. Since the units of lower-levels of design abstraction are transistors or gates, power estimation becomes a slow process at these levels. Therefore designers need to have tools for fast and accurate power estimation at the higher levels of design abstraction such as register transfer level (RTL). A novel RTL power estimation technique called CRAB-RPE will be presented in this thesis. The CRAB power model is built upon four important properties which most of the previous RTL models did not support at the same time. First, the model is based solely on the first and second-order primary input bit-level transition probabilities which provide detailed information about the primary input bit activity dependency of the circuit. Second, the model is based on the power characterization of a microarchitecture library with a complete range of primary input bit transition probabilities without any assumptions about this activity. Third, the pairwise spatial correlations of the primary input nodes are considered by including second-order crossterms of the primary input switching probabilities. Fourth, the first-order temporal correlations of the primary input bits are considered by including 1 to 1 and binary switching transition probabilities. With the proposed model, fast power estimation can be achieved from input bit-level statistics without further simulation. The model was evaluated using the ISCAS combinational circuit benchmarks and other commonly used micro-architectural circuit blocks. Second-order terms were observed to be important for modeling the low bit activity effects on power dissipation. The CRAB power model returned under 5% of the low-level simulator estimates for either biased single, pair PIN statistics or uniform white noise, DBT-like data

Caractérisation automatisée de la consommation de puissance des processeurs pour l'estimation au niveau système

RÉSUMÉ De nos jours, la consommation de puissance est une contrainte clé et une métrique de performance essentielle lors du design des systèmes numériques. La dissipation de chaleur excessive sur les circuits intégrés diminue relativement leurs performances. Également, plus que jamais, nous avons le besoin d’augmenter le temps de vie des batteries de nouvelles électroniques portables. Avec les techniques de design classiques, RTL « Register Transfer Level », une estimation de puissance précise est possible seulement aux dernières étapes du processus de développement. Pour remédier à cette problématique, on a récemment proposé dans la littérature de hausser le niveau d’abstraction de la conception de systèmes embarqués à l’aide de la méthodologie de niveau système « Electronic System Level » (ESL). Dans cette perspective, ce travail propose une méthodologie capable de caractériser automatiquement la consommation de puissance des processeurs configurable de type « soft-processors » et de générer un modèle efficace pour l’estimation de l’énergie consommée au niveau système. À l'aide de ce modèle, une étude comparative entre trois techniques d’estimation est donc présentée. Les résultats de cinq programmes tests montrent une estimation de puissance huit mille fois plus rapide que les techniques d’estimation conventionnelles et une erreur moyenne de seulement ±3.98 % pour le processeur LEON3 et de ±10.70 % pour le processeur Microblaze.----------ABSTRACT Nowadays, power consumption is a key constraint and a digital system design essential metric of performance. Excessive heat dissipation of integrated circuits relatively decreases the performance of the system. Also, more than ever, we need to increase the battery lifetime of new portable electronics. With classical design techniques as RTL « Register Transfer Level », precise power estimation is only possible in the final stages of the development process. To solve this problem, the literature recently proposed to raise the abstraction level of embedded systems design, using ESL « Electronic System Level » methodology. In this context, this project proposes a methodology to automatically characterize configurable soft-processors power consumption and generate an effective power model for energy consumption estimation at system level. Using this model, a comparative study between three estimation techniques is also presented. The results of five benchmarks show that our power estimation is eight thousand times faster than conventional estimation techniques and an average error of only ±3.98 % for the LEON3 processor and ±10.70 % for the Microblaze processor

Energy-efficient design and implementation of turbo codes for wireless sensor network

The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications

High-level Switching Activity Prediction Through Sampled Monitored Simulation

This paper presents a sample-based technique to predict the switching activity of digital circuits. It is an improvement to PowerSC, a SystemC library extension that enables a fast and easy-to-use way of gathering switching activity from SystemC descriptions. The experimental results reveal that it can dramatically reduce the monitoring time of the simulation, with a minimal loss of accuracy with respect to estimates provided by an industrial tool. Several tests realized in a case study with a real-world design obtained reductions in the monitoring time of up to 99% with average errors of no more than 0.05%. © 2005 IEEE.2005161166Klein, F., Azevedo, R., Araujo, G., Enabling High-level Switching Activity Estimation using SystemC (2005), Institute of Computing, UNICAMP, Tech. Rep. IC-05-17, Aug(2003) SystemC Language Reference Manual, , Revision 1.0 ed, SystemC InitiativeLiu, D., Svensson, C., Power consumption estimation in CMOS VLSI chips (1994) IEEE Journal of Solid-State Circuits, pp. 663-670. , JuneK. D. Müller-Glaser, K. Hirsch, and K. Neusinger, Estimating essential design characteristics to support project planning for ASIC design management, L. Goto, SatoshiTrevillyan, Ed. Santa Clara, CA: IEEE Computer Society Press, Nov. 1991, pp. 148-151Xakellis, M.G., Najm, F.N., Statistical estimation of the switching activity in digital circuits (1994) DAC '94: Proceedings of the 31st annual conference on Design automation, pp. 728-733. , ACM PressLandman, P.E., Rabaey, J.M., Activity-sensitive architectural power analysis (1996) IEEE Trans. on Computer-Aided Design of Integrated Circuits, pp. 571-587. , IEEE Computer Society Press, JuneRaghunathan, A., Dey, S., Jha, N.K., Register-transfer level estimation techniques for switching activity and power consumption (1996) Proc. of the 1996 IEEE/ACM international conference on CAD, pp. 158-165. , IEEE Computer SocietyGupta, S., Najm, F.N., Energy and peak-current per-cycle estimation at RTL (2003) IEEE Trans. Very Large Scale Integr. Syst, 11 (4), pp. 525-537Anton, M., Colonescu, I., Macii, E., Poncino, M., Fast characterization of RTL power macromodels (2001) IEEE Proc. of ICECS 2001, pp. 1591-1594Mehta, H., Owens, R.M., Irwin, M.J., Energy characterization based on clustering (1996) DAC '96: Proceedings of the 33rd annual conference on Design automation, pp. 702-707. , ACM PressYe, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., The design and use of SimplePower: A cycle-accurate energy estimation tool (2000) DAC '00: Proceedings of the 37th conference on Design automation, pp. 340-345. , ACM PressPower Compiler User Guide, V-2003.12 ed., Synopsys Inc., December 2003(2004) ModelSim SE 5.8b User's Manual, , Mentor Graphics Corporation, JanuaryMP3 decoder IP www.brazilip.org.br, The Brazil-IP Project, see htt

An Efficient Framework For High-level Power Exploration

Although SystemC is considered the most promising language for system-on-chip functional modeling, it doesn't come with power modeling capabilities. This work presents PowerSC, a novel power estimation framework which instruments SystemC for power characterization, modeling and estimation. Since it is entirely based on SystemC, PowerSC allows consistent power modeling from the highest to the lowest abstraction level. Besides, the framework's API provides facilities to integrate alternative modeling techniques, either at the same or at different abstraction levels. As a result, the required power evaluation infrastructure is reduced to a minimum: the standard SystemC library, the PowerSC library itself and a C++ compiler. Experimental results show both the effectiveness and the efficiency of our framework. On the one hand, two well-known macromodeling techniques were easily integrated into the framework, leading to acceptable average errors at the RT level. On the other hand, library characterization was more than 13x faster as compared to a typical industrial flow. ©2007 IEEE.10461049(2002) SystemC 2.0 User's Guide, , Version 2.0 ed, OSCILiu, D., Svensson, C., Power consumption estimation in CMOS VLSI chips (1994) IEEE Journal of Solid-State Circuits, pp. 663-670. , JuneMüller-Glaser, K.D., Hirsch, K., Neusinger, K., Estimating essential design characteristics to support project planning for ASIC design management (1991) Proc of ICCAD, pp. 148-151. , NovLandman, P.E., Rabaey, J.M., Activity-sensitive architectural power analysis (1996) IEEE Trans. on Computer-Aided Design of Integrated Circuits, pp. 571-587. , JuneMehta, H., Owens, R.M., Irwin, M.J., Energy characterization based on clustering (1996) Proc. of DAC, pp. 702-707Raghunathan, A., Dey, S., Jha, N.K., Register-transfer level estimation techniques for switching activity and power consumption (1996) Proc. of the IEEE/ACM intern. conference on CAD, pp. 158-165Gupta, S., Najm, F.N., Energy and peak-current per-cycle estimation at RTL (2003) IEEE Trans. Very Large Scale Integr. Syst, 11 (4), pp. 525-537Anton, M., Colonescu, I., Macii, E., Poncino, M., Fast characterization of RTL power macromodels (2001) Proc. of ICECSYe, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., The design and use of SimplePower: A cycle-accurate energy estimation tool (2000) Proc. of DAC, pp. 340-345Power Compiler User Guide, X-2005.09 ed., Synopsys Inc., 2005Nebel, W., Helms, D., High-level power estimation and analysis (2005) Low-Power Electronics Design, , CRC Press, ch. 38Stammermann, A., Kruse, L., Nebel, W., Pratsch, A., Schmidt, E., Schulte, M., Schulz, A., System level optimization and design space exploration for low power (2001) Proc. of the 14th international symposium on Systems synthesis, pp. 142-146Klein, F., Azevedo, R., Araujo, G., High-level switching activity prediction through sampled monitored simulation (2005) Proceedings of the International Symposyum on System-on-Chip 2005, , NovemberGupta, S., Najm, F.N., Power macromodeling for high level power estimation (1997) Design Automation Conference, pp. 365-370Macii, E., Poncino, M., Power macro-models for high-level power estimation (2005) Low-Power Electronics Design, , CRC Press, ch. 3