1,502 research outputs found
플래시 메모리를 위한 양방향 비대칭 오류 정정 부호 및 간섭 완화 기법
학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 이정우.Recently, NAND multi-level cell (MLC) flash memories are now widely used due to low cost and high capacity. However, when the number of cell levels increases, cell-to-cell interference (C2CI) which shifts threshold voltage may degrades the error rate in reading process. There are several approaches to alleviate the errors caused by the threshold voltage shift and we discuss error correcting codes and message encoding schemes.
First, we propose error correcting codes that are effective for multi-level cell flash memory and non-binary WOM (write once memory) codes. In particular, we focus on bidirectional error correction codes. The errors in MLC flash memories tend to be directional and limited-magnitude. Many related works focus on asymmetric errors, but bidirectional errors also occur because of the bidirectional interference and the adjustment of the hard-decision reference voltages. The code treats both upward and downward errors when the error magnitude in each direction differs. The maximum magnitudes of the upward error and downward error are lu and ld, respectively. One of proposed codes extends the technique of the distinct sum sets to the bidirectional error correction codes. The other code is bidirectional limited magnitude error correction codes based on modulo operation and uses non-binary conventional error correction codes. These proposed codes can reduce the parity size, and have better error correction performance than the conventional error correction codes when the code rate is equal. Furthermore, error correcting schemes for non-binary WOM codes are discussed. WOM codes is a coding scheme that allows information to be written in a memory cell multiple times without erasure, and conventional error correction codes cannot be directly applied to WOM codes. The advantages of the proposed methods are that these are practical and systematic codes, and the complexity of encoding and decoding processes are low. We also introduce effective error locating limited-magnitude parity check error correction codes for the MLC flash memory error with lower complexity.
Second, we introduce coding schemes to lower the generated interferences by cell to cell interference. It is known that C2CI is caused by the threshold voltage change of neighbor cells in writing operation. The amount of threshold voltage change is proportional to the magnitude. To minimize the generated interference, the average magnitude needs to be decreased. We propose two new C2CI reduction coding schemes that adjust the average magnitude to reduce C2CI. The proposed coding scheme deals with q-ary message codes, and generates fixed length codes. Message codewords are divided into several blocks, and are modified by modulo addition with proper values to minimize the average magnitude. We also propose low energy Huffman codes based on entropy coding when the frequency of symbols is not distributed uniformly. This scheme produces variable-length codes without redundancy. We modified Huffman codes to minimize average number of high bits ('1' bits). We show that proposed codes generate optimal codewords which have minimum high bits with minimum average codeword length.Chapter 1 Introduction 1
1.1 Backgrounds 1
1.2 Scope and Organization 5
Chapter 2 MLC Flash Memory Interference and Mitigation Techniques for Reliability 9
2.1 MLC flash memory and interference 9
2.2 Signal processing based interference mitigation in MLC flash memories 15
2.3 WOM codes 22
2.4 Asymmetric limited-magitude error correction codes based on distinct sum set 27
Chapter 3 Error Correction Codes for Flash Memories 29
3.1 Introduction 29
3.2 Bidirectional error correction codes for non-binary WOM codes based on distinct sum sets 30
3.2.1 Bidirectional error correction codes based on distinct sum sets 30
3.2.2 Error correction coding schemes for WOM codes based on distinct sum sets 41
3.3 Bidirectional error correction codes for WOM codes based on modulo operation 44
3.3.1 Bidirectional error correction codes based on modulo operation 44
3.3.2 Performance simulation of bidirectional error correction codes based on modulo operation 54
3.3.3 Error correction coding schemes for WOM codes based on modulo operation 58
3.4 Performance of error correction coding schemes for WOM code 61
3.5 Error locating parity check codes for errors with limited magnitude 68
3.6 Summary 77
Chapter 4 On Interference Mitigating Codes for Multi-level Flash Memories 79
4.1 Introduction 79
4.2 The modeling of generated interference in flash memory 80
4.3 Coding schemes for interference mitigation 83
4.3.1 Minimum energy coding 83
4.3.2 Module shift coding 85
4.3.3 Low energy Huffman code 89
4.4 Performance analysis of proposed coding schemes 91
4.4.1 Performance analysis of ME codes 91
4.4.2 Performance analysis of MS codes 93
4.4.3 Performance of low-energy Huffman codes 97
4.4.4 C2CI reduction performance 99
4.5 Summary 102
Chapter 5 Conclusions 105
Appendix A 109
A.1 Performance analysis of MS coding with eta=2 case in chap. 4.4.2. 109
Bibliography 113
Abstract in Korean 120Docto
Rewriting Flash Memories by Message Passing
This paper constructs WOM codes that combine rewriting and error correction
for mitigating the reliability and the endurance problems in flash memory. We
consider a rewriting model that is of practical interest to flash applications
where only the second write uses WOM codes. Our WOM code construction is based
on binary erasure quantization with LDGM codes, where the rewriting uses
message passing and has potential to share the efficient hardware
implementations with LDPC codes in practice. We show that the coding scheme
achieves the capacity of the rewriting model. Extensive simulations show that
the rewriting performance of our scheme compares favorably with that of polar
WOM code in the rate region where high rewriting success probability is
desired. We further augment our coding schemes with error correction
capability. By drawing a connection to the conjugate code pairs studied in the
context of quantum error correction, we develop a general framework for
constructing error-correction WOM codes. Under this framework, we give an
explicit construction of WOM codes whose codewords are contained in BCH codes.Comment: Submitted to ISIT 201
Trajectory Codes for Flash Memory
Flash memory is well-known for its inherent asymmetry: the flash-cell charge
levels are easy to increase but are hard to decrease. In a general rewriting
model, the stored data changes its value with certain patterns. The patterns of
data updates are determined by the data structure and the application, and are
independent of the constraints imposed by the storage medium. Thus, an
appropriate coding scheme is needed so that the data changes can be updated and
stored efficiently under the storage-medium's constraints.
In this paper, we define the general rewriting problem using a graph model.
It extends many known rewriting models such as floating codes, WOM codes,
buffer codes, etc. We present a new rewriting scheme for flash memories, called
the trajectory code, for rewriting the stored data as many times as possible
without block erasures. We prove that the trajectory code is asymptotically
optimal in a wide range of scenarios.
We also present randomized rewriting codes optimized for expected performance
(given arbitrary rewriting sequences). Our rewriting codes are shown to be
asymptotically optimal.Comment: Submitted to IEEE Trans. on Inform. Theor
Using Short Synchronous WOM Codes to Make WOM Codes Decodable
In the framework of write-once memory (WOM) codes, it is important to
distinguish between codes that can be decoded directly and those that require
that the decoder knows the current generation to successfully decode the state
of the memory. A widely used approach to construct WOM codes is to design first
nondecodable codes that approach the boundaries of the capacity region, and
then make them decodable by appending additional cells that store the current
generation, at an expense of a rate loss. In this paper, we propose an
alternative method to make nondecodable WOM codes decodable by appending cells
that also store some additional data. The key idea is to append to the original
(nondecodable) code a short synchronous WOM code and write generations of the
original code and of the synchronous code simultaneously. We consider both the
binary and the nonbinary case. Furthermore, we propose a construction of
synchronous WOM codes, which are then used to make nondecodable codes
decodable. For short-to-moderate block lengths, the proposed method
significantly reduces the rate loss as compared to the standard method.Comment: To appear in IEEE Transactions on Communications. The material in
this paper was presented in part at the 2012 IEEE International Symposium on
Information Theory, Cambridge, MA, July 201
Rewriting Codes for Joint Information Storage in Flash Memories
Memories whose storage cells transit irreversibly between
states have been common since the start of the data storage
technology. In recent years, flash memories have become a very
important family of such memories. A flash memory cell has q
states—state 0.1.....q-1 - and can only transit from a lower
state to a higher state before the expensive erasure operation takes
place. We study rewriting codes that enable the data stored in a
group of cells to be rewritten by only shifting the cells to higher
states. Since the considered state transitions are irreversible, the
number of rewrites is bounded. Our objective is to maximize the
number of times the data can be rewritten. We focus on the joint
storage of data in flash memories, and study two rewriting codes
for two different scenarios. The first code, called floating code, is for
the joint storage of multiple variables, where every rewrite changes
one variable. The second code, called buffer code, is for remembering
the most recent data in a data stream. Many of the codes
presented here are either optimal or asymptotically optimal. We
also present bounds to the performance of general codes. The results
show that rewriting codes can integrate a flash memory’s
rewriting capabilities for different variables to a high degree
Coding Techniques for Error Correction and Rewriting in Flash Memories
Flash memories have become the main type of non-volatile memories. They
are widely used in mobile, embedded and mass-storage devices. Flash memories store
data in floating-gate cells, where the amount of charge stored in cells – called cell levels
– is used to represent data. To reduce the level of any cell, a whole cell block (about
106 cells) must be erased together and then reprogrammed. This operation, called
block erasure, is very costly and brings significant challenges to cell programming and
rewriting of data. To address these challenges, rank modulation and rewriting codes
have been proposed for reliably storing and modifying data. However, for these new
schemes, many problems still remain open.
In this work, we study error-correcting rank-modulation codes and rewriting
codes for flash memories. For the rank modulation scheme, we study a family of one-
error-correcting codes, and present efficient encoding and decoding algorithms. For
rewriting, we study a family of linear write-once memory (WOM) codes, and present
an effective algorithm for rewriting using the codes. We analyze the performance of
our solutions for both schemes
RFID Key Establishment Against Active Adversaries
We present a method to strengthen a very low cost solution for key agreement
with a RFID device.
Starting from a work which exploits the inherent noise on the communication
link to establish a key by public discussion, we show how to protect this
agreement against active adversaries. For that purpose, we unravel integrity
-codes suggested by Cagalj et al.
No preliminary key distribution is required.Comment: This work was presented at the First IEEE Workshop on Information
Forensics and Security (WIFS'09) (update including minor remarks and
references to match the presented version
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