Program latihan industri di Kolej Universiti Teknologi Tun Hussein Onn : kajian terhadap perlaksanaan sistem penilaian

Kajian yang dijalankan adalah bertajuk "Program Lalilian lndustri Di Kolej Universiti Teknologi Tun Hussein Onn : Kajian Terhadap Perlaksanaan Sistem Penilaian". Sampel terdin daripada 6 orang pakar serta 63 orang pelajar yang terlibat dalam latihan industri. Maklumat yang diperolehi berdasarkan kaedah kualitatif dan kuantitatif Data dianalisis untuk meninjau kaedah penilaian yang dijalankan dan seterusnya memastikan apakali sistem penilaian yang perlu diperbaiki. Secara keseluruhannya, kebanyakan responden berpendapat bahawa sistem penilaian yang sedia ada adalah perlu diperbaki dan disistematikkan selaras dengan ISO 9000 : 2001. Berdasarkan daripada keputusan yang diperolehi dan bimbingnan pakar dari Unit Latihan lndustri KUiTTHO, maka satu "Buku Panduan Penilaian Latihan lndustri" dihasilkan dengan panduan yang ringkas dan lampiran borang-borang yang telah diperbaiki dan diubahsuai. Diharapkan produk mi dapat digunakan untuk masa-masa akan datang

A FPGA system for QRS complex detection based on Integer Wavelet Transform

Due to complexity of their mathematical computation, many QRS detectors are implemented in software and cannot operate in real time. The paper presents a real-time hardware based solution for this task. To filter ECG signal and to extract QRS complex it employs the Integer Wavelet Transform. The system includes several components and is incorporated in a single FPGA chip what makes it suitable for direct embedding in medical instruments or wearable health care devices. It has sufficient accuracy (about 95%), showing remarkable noise immunity and low cost. Additionally, each system component is composed of several identical blocks/cells what makes the design highly generic. The capacity of today existing FPGAs allows even dozens of detectors to be placed in a single chip. After the theoretical introduction of wavelets and the review of their application in QRS detection, it will be shown how some basic wavelets can be optimized for easy hardware implementation. For this purpose the migration to the integer arithmetic and additional simplifications in calculations has to be done. Further, the system architecture will be presented with the demonstrations in both, software simulation and real testing. At the end, the working performances and preliminary results will be outlined and discussed. The same principle can be applied with other signals where the hardware implementation of wavelet transform can be of benefit

Fault Diagnosis for Power Electronics Converters based on Deep Feedforward Network and Wavelet Compression

A fault diagnosis method for power electronics converters based on deep feedforward network and wavelet compression is proposed in this paper. The transient historical data after wavelet compression are used to realize the training of fault diagnosis classifier. Firstly, the correlation analysis of the voltage or current data running in various fault states is performed to remove the redundant features and the sampling point. Secondly, the wavelet transform is used to remove the redundant data of the features, and then the training sample data is greatly compressed. The deep feedforward network is trained by the low frequency component of the features, while the training speed is greatly accelerated. The average accuracy of fault diagnosis classifier can reach over 97%. Finally, the fault diagnosis classifier is tested, and final diagnosis result is determined by multiple-groups transient data, by which the reliability of diagnosis results is improved. The experimental result proves that the classifier has strong generalization ability and can accurately locate the open-circuit faults in IGBTs.Comment: Electric Power Systems Researc

Wavelet Transform for Real-Time Detection of Action Potentials in Neural Signals

We present a study on wavelet detection methods of neuronal action potentials (APs). Our final goal is to implement the selected algorithms on custom integrated electronics for on-line processing of neural signals; therefore we take real-time computing as a hard specification and silicon area as a price to pay. Using simulated neural signals including APs, we characterize an efficient wavelet method for AP extraction by evaluating its detection rate and its implementation cost. We compare software implementation for three methods: adaptive threshold, discrete wavelet transform (DWT), and stationary wavelet transform (SWT). We evaluate detection rate and implementation cost for detection functions dynamically comparing a signal with an adaptive threshold proportional to its SD, where the signal is the raw neural signal, respectively: (i) non-processed; (ii) processed by a DWT; (iii) processed by a SWT. We also use different mother wavelets and test different data formats to set an optimal compromise between accuracy and silicon cost. Detection accuracy is evaluated together with false negative and false positive detections. Simulation results show that for on-line AP detection implemented on a configurable digital integrated circuit, APs underneath the noise level can be detected using SWT with a well-selected mother wavelet, combined to an adaptive threshold

Hilbert Based Testing of ADC Differential Non-linearity Using Wavelet Transform Algorithms

In testing Mixed Signal Devices such as Analog to Digital and Digital to Analog Converters, some dynamic parameters, such as Differential Non-Linearity and Integral Non-linearity, are very critical to evaluating devises performance. However, such analysis has been notorious for complexity and massive compiling process. Therefore, this research will focus on testing dynamic parameters such as Differential Non-Linearity by simulating numerous numbers of bits Analog to Digital Converters and test the output signals base on new testing algorithms of Wavelet transform based on Hilbert process. Such a new testing algorithm should enhance the testing process by using less compiling data samples and prompt testing results. In addition, new testing results will be compared with the conventional testing process of Histogram algorithms for accuracy and enactment

Efficient architectures and power modelling of multiresolution analysis algorithms on FPGA

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In the past two decades, there has been huge amount of interest in Multiresolution Analysis Algorithms (MAAs) and their applications. Processing some of their applications such as medical imaging are computationally intensive, power hungry and requires large amount of memory which cause a high demand for efficient algorithm implementation, low power architecture and acceleration. Recently, some MAAs such as Finite Ridgelet Transform (FRIT) Haar Wavelet Transform (HWT) are became very popular and they are suitable for a number of image processing applications such as detection of line singularities and contiguous edges, edge detection (useful for compression and feature detection), medical image denoising and segmentation. Efficient hardware implementation and acceleration of these algorithms particularly when addressing large problems are becoming very chal-lenging and consume lot of power which leads to a number of issues including mobility, reliability concerns. To overcome the computation problems, Field Programmable Gate Arrays (FPGAs) are the technology of choice for accelerating computationally intensive applications due to their high performance. Addressing the power issue requires optimi- sation and awareness at all level of abstractions in the design flow. The most important achievements of the work presented in this thesis are summarised here. Two factorisation methodologies for HWT which are called HWT Factorisation Method1 and (HWTFM1) and HWT Factorasation Method2 (HWTFM2) have been explored to increase number of zeros and reduce hardware resources. In addition, two novel efficient and optimised architectures for proposed methodologies based on Distributed Arithmetic (DA) principles have been proposed. The evaluation of the architectural results have shown that the proposed architectures results have reduced the arithmetics calculation (additions/subtractions) by 33% and 25% respectively compared to direct implementa-tion of HWT and outperformed existing results in place. The proposed HWTFM2 is implemented on advanced and low power FPGA devices using Handel-C language. The FPGAs implementation results have outperformed other existing results in terms of area and maximum frequency. In addition, a novel efficient architecture for Finite Radon Trans-form (FRAT) has also been proposed. The proposed architecture is integrated with the developed HWT architecture to build an optimised architecture for FRIT. Strategies such as parallelism and pipelining have been deployed at the architectural level for efficient im-plementation on different FPGA devices. The proposed FRIT architecture performance has been evaluated and the results outperformed some other existing architecture in place. Both FRAT and FRIT architectures have been implemented on FPGAs using Handel-C language. The evaluation of both architectures have shown that the obtained results out-performed existing results in place by almost 10% in terms of frequency and area. The proposed architectures are also applied on image data (256 £ 256) and their Peak Signal to Noise Ratio (PSNR) is evaluated for quality purposes. Two architectures for cyclic convolution based on systolic array using parallelism and pipelining which can be used as the main building block for the proposed FRIT architec-ture have been proposed. The first proposed architecture is a linear systolic array with pipelining process and the second architecture is a systolic array with parallel process. The second architecture reduces the number of registers by 42% compare to first architec-ture and both architectures outperformed other existing results in place. The proposed pipelined architecture has been implemented on different FPGA devices with vector size (N) 4,8,16,32 and word-length (W=8). The implementation results have shown a signifi-cant improvement and outperformed other existing results in place. Ultimately, an in-depth evaluation of a high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called func-tional level power modelling approach have been presented. The mathematical techniques that form the basis of the proposed power modeling has been validated by a range of custom IP cores. The proposed power modelling is scalable, platform independent and compares favorably with existing approaches. A hybrid, top-down design flow paradigm integrating functional level power modelling with commercially available design tools for systematic optimisation of IP cores has also been developed. The in-depth evaluation of this tool enables us to observe the behavior of different custom IP cores in terms of power consumption and accuracy using different design methodologies and arithmetic techniques on virous FPGA platforms. Based on the results achieved, the proposed model accuracy is almost 99% true for all IP core's Dynamic Power (DP) components.Thomas Gerald Gray Charitable Trus

Artificial Neural Network and Wavelet Features Extraction Applications in Nitrate and Sulphate Water Contamination Estimation

This work expounds the review of non-destructive evaluation using near-field sensors and its application in environmental monitoring. Star array configuration of planar electromagnetic sensor is explained in this work for nitrate and sulphate detection in water. The experimental results show that the star array planar electromagnetic sensor was able to detect nitrate and sulphate at different concentrations. Artificial Neural Networks (ANN) is used to classify different levels of nitrate and sulphate contaminations in water sources. The star array planar electromagnetic sensors were subjected to different water samples contaminated by nitrate and sulphate. Classification using Wavelet Transform (WT) was applied to extract the output signals features. These features were fed to ANN consequently, for the classification of different levels of nitrate and sulphate concentration in water. The model is capable of distinguishing the concentration level in the presence of other types of contamination with a root mean square error (RMSE) of 0.0132 or 98.68% accuracy