Acceleration of hardware code coverage closure using machine learning

Abstract. With the ever-increasing system-on-chip (SoC) design complexity, the verification of such systems is becoming more and more challenging and extremely time consuming. Hence, the human efforts put in this task seem neither to be sufficient, nor efficient enough anymore to maintain a good pace with the escalating market demands. In this work, we will present a descent way of utilizing machine learning (ML) for reducing the overhead of hardware design verification in terms of resources consumption. Our focus in this thesis is especially about the time spent on coverage closure that usually occupies a great deal of the whole verification time. Both deep learning (DL) and reinforcement learning (RL) are deployed for this purpose, in two different experiments, in order to come out with the most coherent way to accomplish the coverage closure task. On one hand, neural networks (NNs) were used to help visualize whether a stimulus is worth to run the simulation with, by predicting the coverage number that it would generate. On the other hand, Q-learning was used to predict the minimal set of tests needed to reach some code coverage goal, by optimizing and reducing the set of tests while still achieving the same coverage levels. The results of these experiments show captivating findings. First, the root mean square error (RMSE) of the neural network models was about 3 and 5 in predicting two different coverage values, respectively, which is quite good for a training run on a small dataset. Second, our Q-agent was able to do better than the coverage ranking utility of the simulation tool by almost 43%, where it reduced the number of tests from 63, as suggested by the simulator, to 36. This should remarkably reduce the required number of simulations in weekly regressions, hence result in a huge gain in time and resources. Both of these approaches aim at reducing the engineers’ efforts through accelerating the verification process and automating it, which frees some of the engineers’ time and allow them to focus on more important matters

Formal methods for functional verification of cache-coherent systems-on-chip

State-of-the-art System-on-Chip (SoC) architectures integrate many different components, such as processors, accelerators, memories, and I/O blocks. Some of those components, but not all, may have caches. Because the effort of validation with simulation-based techniques, currently used in industry, grows exponentially with the complexity of the SoC, this thesis investigates the use of formal verification techniques in this context. More precisely, we use the CADP toolbox to develop and validate a generic formal model of a heterogeneous cache-coherent SoC compliant with the recent AMBA 4 ACE specification proposed by ARM. We use a constraint-oriented specification style to model the general requirements of the specification. We verify system properties on both the constrained and unconstrained model to detect the cache coherency corner cases. We take advantage of the parametrization of the proposed model to produce a comprehensive set of counterexamples of non-satisfied properties in the unconstrained model. The results of formal verification are then used to improve the industrial simulation-based verification techniques in two aspects. On the one hand, we suggest using the formal model to assess the sanity of an interface verification unit. On the other hand, in order to generate clever semi-directed test cases from temporal logic properties, we propose a two-step approach. One step consists in generating system-level abstract test cases using model-based testing tools of the CADP toolbox. The other step consists in refining those tests into interface-level concrete test cases that can be executed at RTL level with a commercial Coverage-Directed Test Generation tool. We found that our approach helps in the transition between interface-level and system-level verification, facilitates the validation of system-level properties, and enables early detection of bugs in both the SoC and the commercial test-bench.Les architectures des systèmes sur puce (System-on-Chip, SoC) actuelles intègrent de nombreux composants différents tels que les processeurs, les accélérateurs, les mémoires et les blocs d'entrée/sortie, certains pouvant contenir des caches. Vu que l'effort de validation basée sur la simulation, actuellement utilisée dans l'industrie, croît de façon exponentielle avec la complexité des SoCs, nous nous intéressons à des techniques de vérification formelle. Nous utilisons la boîte à outils CADP pour développer et valider un modèle formel d'un SoC générique conforme à la spécification AMBA 4 ACE récemment proposée par ARM dans le but de mettre en œuvre la cohérence de cache au niveau système. Nous utilisons une spécification orientée contraintes pour modéliser les exigences générales de cette spécification. Les propriétés du système sont vérifié à la fois sur le modèle avec contraintes et le modèle sans contraintes pour détecter les cas intéressants pour la cohérence de cache. La paramétrisation du modèle proposé a permis de produire l'ensemble complet des contre-exemples qui ne satisfont pas une certaine propriété dans le modèle non contraint. Notre approche améliore les techniques industrielles de vérification basées sur la simulation en deux aspects. D'une part, nous suggérons l'utilisation du modèle formel pour évaluer la bonne construction d'une unité de vérification d'interface. D'autre part, dans l'objectif de générer des cas de test semi-dirigés intelligents à partir des propriétés de logique temporelle, nous proposons une approche en deux étapes. La première étape consiste à générer des cas de tests abstraits au niveau système en utilisant des outils de test basé sur modèle de la boîte à outils CADP. La seconde étape consiste à affiner ces tests en cas de tests concrets au niveau de l'interface qui peuvent être exécutés en RTL grâce aux services d'un outil commercial de génération de tests dirigés par les mesures de couverture. Nous avons constaté que notre approche participe dans la transition entre la vérification du niveau interface, classiquement pratiquée dans l'industrie du matériel, et la vérification au niveau système. Notre approche facilite aussi la validation des propriétés globales du système, et permet une détection précoce des bugs, tant dans le SoC que dans les bancs de test commerciales

FAA Center of Excellence for Alternative Jet Fuels & Environment: Annual Technical Report 2021: For the Period October 1, 2020 - September 30, 2021: Volume 2

FAA Award Number 13-C.This report covers the period October 1, 2020, through September 30, 2021. The Center was established by the authority of FAA solicitation 13-C-AJFE-Solicitation. During that time the ASCENT team launched a new website, which can be viewed at ascent.aero. The next meeting will be held April 5-7, 2022, in Alexandria, VA

7th International Conference on Higher Education Advances (HEAd'21)

Information and communication technologies together with new teaching paradigms are reshaping the learning environment.The International Conference on Higher Education Advances (HEAd) aims to become a forum for researchers and practitioners to exchange ideas, experiences,opinions and research results relating to the preparation of students and the organization of educational systems.Doménech I De Soria, J.; Merello Giménez, P.; Poza Plaza, EDL. (2021). 7th International Conference on Higher Education Advances (HEAd'21). Editorial Universitat Politècnica de València. https://doi.org/10.4995/HEAD21.2021.13621EDITORIA

Interrupt-generating active data objects

An investigation is presented into an interrupt-generating object model which is designed to reduce the effort of programming distributed memory multicomputer networks. The object model is aimed at the natural modelling of problem domains in which a number of concurrent entities interrupt one another as they lay claim to shared resources. The proposed computational model provides for the safe encapsulation of shared data, and incorporates inherent arbitration for simultaneous access to the data. It supplies a predicate triggering mechanism for use in conditional synchronization and as an alternative mechanism to polling. Linguistic support for the proposal requires a novel form of control structure which is able to interface sensibly with interrupt-generating active data objects. The thesis presents the proposal as an elemental language structure, with axiomatic guarantees which enforce safety properties and aid in program proving. The established theory of CSP is used to reason about the object model and its interface. An overview is presented of a programming language called HUL, whose semantics reflect the proposed computational model. Using the syntax of HUL, the application of the interrupt-generating active data object is illustrated. A range of standard concurrent problems is presented to demonstrate the properties of the interrupt-generating computational model. Furthermore, the thesis discusses implementation considerations which enable the model to be mapped precisely onto multicomputer networks, and which sustain the abstract programming level provided by the interrupt-generating active data object in the wider programming structures of HUL

Cadres, gangs and prophets: the commodity futures markets of China

In China's market reforms, the emergence of commodity futures markets marked the way in which the country took up more sophisticated components of capitalist markets. Based on seven months of ethnographic fieldwork in 2005, this thesis is the first ethnography conducted in the commodity futures markets of China. It provides field records of the relationship between state structures, quasi-public organisations and the private sector in a post-Communist market. It shows how social groups align to form capital factions, and how these factions attempt to calculate the actions of each other. It also provides an account of how knowledge is circulated, and how reputation, authority and expertise are developed within the markets. The author argues that the notion of"performativity" can be applied to the case of Chinese futures markets. The consensus held by market actors and their subsequent actions are a major contribution to market reality. In the context of Chinese markets. political power plays a particularly crucial role-it links up a politicized feedback loop between perception, action and reality. The thesis applies the concept of technology transfer to assess whether futures markets have an inherent "script" that unfolds and is implemented under different social, cultural and political contexts. Relaxing assumptions held by neoclassical economists (such as individualized rationality), the author believes that the feedback loop of knowledge, action and reality is th e "vanilla core" of markets. One of the key factors in success in market construction is the successful implementation of s.uch feedback loops