Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability.

The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the shrinking of the dimensions of silicon transistor devices, as a way to improve the cost and performance of electronic devices. However, several design challenges have emerged as transistors have become smaller. For instance, wires are not scaling as fast as transistors, and delay associated with wires is becoming more significant. Moreover, in the design flow for integrated circuits, accurate modeling of wire-related delay is available only toward the end of the design process, when the physical placement of logic units is known. Consequently, one can only know whether timing performance objectives are satisfied, i.e., if timing closure is achieved, after several design optimizations. Unless timing closure is achieved, time-consuming design-flow iterations are required. Given the challenges arising from increasingly complex designs, failing to quickly achieve timing closure threatens the ability of designers to produce high-performance chips that can match continually growing consumer demands. In this dissertation, we introduce powerful constraint-guided synthesis optimizations that take into account upcoming timing closure challenges and eliminate expensive design iterations. In particular, we use logic simulation to approximate the behavior of increasingly complex designs leveraging a recently proposed concept, called bit signatures, which allows us to represent a large fraction of a complex circuit's behavior in a compact data structure. By manipulating these signatures, we can efficiently discover a greater set of valid logic transformations than was previously possible and, as a result, enhance timing optimization. Based on the abstractions enabled through signatures, we propose a comprehensive suite of novel techniques: (1) a fast computation of circuit don't-cares that increases restructuring opportunities, (2) a verification methodology to prove the correctness of speculative optimizations that efficiently utilizes the computational power of modern multi-core systems, and (3) a physical synthesis strategy using signatures that re-implements sections of a critical path while minimizing perturbations to the existing placement. Our results indicate that logic simulation is effective in approximating the behavior of complex designs and enables a broader family of optimizations than previous synthesis approaches.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/61793/1/splaza_1.pd

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Modern FPGA placement techniques with hardware acceleration

In deep sub-micron technology nodes, Application-Specific Integrated Circuits (ASICs) are becoming expensive to design and manufacture. For this reason, Field Programmable Gate Arrays (FPGAs), which are general purpose and flexible programmable hardware, are gaining more design wins in low volume and fast evolving applications. Modern FPGAs are becoming popular in high performance data analytics, search engines, autonomous cars, communication and networking applications. FPGAs are also accompanied with a complete Computer-Aided Design (CAD) toolchain, that is used to optimally map and fit the design applications or workloads onto the underlying target FPGA device. These design applications mapped onto the FPGA demand high maximum achievable clock frequency (Fmax) and low power consumption while maintaining a low compilation time, which is a major hindrance in widespread adoption of FPGAs. The focus of this Ph.D. dissertation is the placement problem for FPGAs, which takes a major portion of the FPGA CAD tool runtime. A new algorithm for spreading cells during FPGA global placement is proposed, which achieves better wirelength and routing congestion and takes less runtime than the algorithm used in the state-of-the-art academic FPGA placer. We also propose FPGA acceleration of various subsystems of an analytic global placement algorithm, including wirelength gradient computation and spreading, which achieves significant speedup over the multi-threaded CPU version. A new detailed placement algorithm is proposed, which offers better tradeoff between quality and runtime compared to existing methods. This algorithm is also accelerated on a GPU and an FPGA, achieving significant speedup over multi-threaded CPU implementation. Another detailed placement algorithm is also proposed which physically re-aligns timing critical paths and improves Fmax with minimal runtime overhead. Both of these algorithms for detailed placement have shown good results on industrial benchmarks and have been integrated into an industrial FPGA CAD tool flowElectrical and Computer Engineerin

Timing-Driven Macro Placement

Placement is an important step in the process of finding physical layouts for electronic computer chips. The basic task during placement is to arrange the building blocks of the chip, the circuits, disjointly within a given chip area. Furthermore, such positions should result in short circuit interconnections which can be routed easily and which ensure all signals arrive in time. This dissertation mostly focuses on macros, the largest circuits on a chip. In order to optimize timing characteristics during macro placement, we propose a new optimistic timing model based on geometric distance constraints. This model can be computed and evaluated efficiently in order to predict timing traits accurately in practice. Packing rectangles disjointly remains strongly NP-hard under slack maximization in our timing model. Despite of this we develop an exact, linear time algorithm for special cases. The proposed timing model is incorporated into BonnMacro, the macro placement component of the BonnTools physical design optimization suite developed at the Research Institute for Discrete Mathematics. Using efficient formulations as mixed-integer programs we can legalize macros locally while optimizing timing. This results in the first timing-aware macro placement tool. In addition, we provide multiple enhancements for the partitioning-based standard circuit placement algorithm BonnPlace. We find a model of partitioning as minimum-cost flow problem that is provably as small as possible using which we can avoid running time intensive instances. Moreover we propose the new global placement flow Self-Stabilizing BonnPlace. This approach combines BonnPlace with a force-directed placement framework. It provides the flexibility to optimize the two involved objectives, routability and timing, directly during placement. The performance of our placement tools is confirmed on a large variety of academic benchmarks as well as real-world designs provided by our industrial partner IBM. We reduce running time of partitioning significantly and demonstrate that Self-Stabilizing BonnPlace finds easily routable placements for challenging designs – even when simultaneously optimizing timing objectives. BonnMacro and Self-Stabilizing BonnPlace can be combined to the first timing-driven mixed-size placement flow. This combination often finds placements with competitive timing traits and even outperforms solutions that have been determined manually by experienced designers

Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning

International audienceIn the physical synthesis of integrated circuits the legalization step may move all circuit cells to fix overlaps and misalignments. While doing so, it should cause the smallest perturbation possible to the solution found by previous optimization steps to preserve placement quality. Legalization techniques must handle circuits with millions of cells within acceptable runtimes, besides facing other issues such as mixed-cell-height and fence regions. In this work we propose a k-d tree data structure to partition the circuit, thus removing data dependency. Then, legalization is sped up through both input size reduction and parallel execution. As a use case we employed a modified version of the classic legalization algorithm Abacus. Our solution achieved a maximum speedup of 35 times over a sequential version of Abacus for the circuits of the ICCAD2015 CAD contest. It also provided up to 10% reduction on the average cell displacement

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Portugal SB13: contribution of sustainable building to meet EU 20-20-20 targets

Proceedings of the International Conference Portugal SB13: contribution of sustainable building to meet EU 20-20-20 targetsThe international conference Portugal SB13 is organized by the University of Minho, the Technical University of Lisbon and the Portuguese Chapter of the International Initiative for a Sustainable Built Environment in Guimarães, Portugal, from the 30th of October till the 1st of November 2013. This conference is included in the Sustainable Building Conference Series 2013-2014 (SB13-14) that are being organized all over the world. The event is supported by high prestige partners, such as the International Council for Research and Innovation in Building and Construction (CIB), the United Nations Environment Programme (UNEP), the International Federation of Consulting Engineers (FIDIC) and the International Initiative for a Sustainable Built Environment (iiSBE). Portugal SB13 is focused on the theme â Sustainable Building Contribution to Achieve the European Union 20-20-20 Targetsâ . These targets, known as the â EU 20-20-20â targets, set three key objectives for 2020: - A 20% reduction in EU greenhouse gas emissions from 1990 levels; - Raising the share of EU energy consumption produced from renewable resources to 20%; - A 20% improvement in the EU's energy efficiency. Building sector uses about 40% of global energy, 25% of global water, 40% of global resources and emit approximately 1/3 of the global greenhouse gas emissions (the largest contributor). Residential and commercial buildings consume approximately 60% of the worldâ s electricity. Existing buildings represent significant energy saving opportunities because their performance level is frequently far below the current efficiency potentials. Energy consumption in buildings can be reduced by 30 to 80% using proven and commercially available technologies. Investment in building energy efficiency is accompanied by significant direct and indirect savings, which help offset incremental costs, providing a short return on investment period. Therefore, buildings offer the greatest potential for achieving significant greenhouse gas emission reductions, at least cost, in developed and developing countries. On the other hand, there are many more issues related to the sustainability of the built environment than energy. The building sector is responsible for creating, modifying and improving the living environment of the humanity. Construction and buildings have considerable environmental impacts, consuming a significant proportion of limited resources of the planet including raw material, water, land and, of course, energy. The building sector is estimated to be worth 10% of global GDP (5.5 trillion EUR) and employs 111 million people. In developing countries, new sustainable construction opens enormous opportunities because of the population growth and the increasing prosperity, which stimulate the urbanization and the construction activities representing up to 40% of GDP. Therefore, building sustainably will result in healthier and more productive environments. The sustainability of the built environment, the construction industry and the related activities are a pressing issue facing all stakeholders in order to promote the Sustainable Development. The Portugal SB13 conference topics cover a wide range of up-to-date issues and the contributions received from the delegates reflect critical research and the best available practices in the Sustainable Building field. The issues presented include: - Nearly Zero Energy Buildings - Policies for Sustainable Construction - High Performance Sustainable Building Solutions - Design and Technologies for Energy Efficiency - Innovative Construction Systems - Building Sustainability Assessment Tools - Renovation and Retrofitting - Eco-Efficient Materials and Technologies - Urban Regeneration - Design for Life Cycle and Reuse - LCA of sustainable materials and technologies All the articles selected for presentation at the conference and published in these Proceedings, went through a refereed review process and were evaluated by, at least, two reviewers. The Organizers want to thank all the authors who have contributed with papers for publication in the proceedings and to all reviewers, whose efforts and hard work secured the high quality of all contributions to this conference. A special gratitude is also addressed to Eng. José Amarílio Barbosa and to Eng. Catarina Araújo that coordinated the Secretariat of the Conference. Finally, Portugal SB13 wants to address a special thank to CIB, UNEP, FIDIC and iiSBE for their support and wish great success for all the other SB13 events that are taking place all over the world