Architectural implementation of cordic unit and its applications

The ubiquity of DSP has made increasing demand to develop area efficient and accurate architectures in carrying out many nonlinear arithmetic operations. One such architecture is CORDIC unit which has many applications in the field of DSP including implementing transforms based on Fourier basis. This report presents architecture of CORDIC, embedded with a scaling unit that has only minimal number of adders and shifters. It can be implemented in rotation mode as well as vectoring mode. The purpose of the design is to get a scaling free CORDIC unit preserving the design of original algorithm. The proposed design has a considerable reduction in hardware when compared with other scaling free architectures. The analysis of error for different word lengths and different input ranges for fixed word length gives a better choice to choose the parameters. The error in rotation mode for 16 bit data path, obtained for Y equivalent input is 0.073% and for X equivalent input is 0.067%. We also report architecture of a DFT core that is implemented using low latency CORDIC. A scaling unit has been included to get scaled outputs. The reported DFT core architecture has 22 adders in total, in addition to 2 CORDIC units. DDS or NCO are nowadays prominently used in the applications of RF signal processing, satellite communications, etc. This report also brings out the FPGA implementation of one such DDS which has quadrature outputs. The proposed DDS design, which is based on pipelined CORDIC, has considerable improvement in terms of SFDR compared to other existing designs at reduced hardware. This report also proposes multiplier-less architecture for the implementation of radix-2^2 folded pipelined complex FFT core based on CORDIC technique. The number of points considered in the work is sixteen and the folding is done by a factor of four

CORDICのハードウェア構成及び応用に関する研究

電気通信大学201

A smart monitoring system for bearing fault detection

Rolling element bearings are commonly used in rotating machinery to support shafts, reduce friction, and increase power transmission efficiency. For a machinery system, bearing fault could be the most possible cause of mechanical failures. If bearing defect can be detected at its early stage, mechanical performance degradation and even economic losses can be avoided. Although many signal processing techniques have been proposed in the literature for bearing fault detection, reliable bearing fault diagnosis is still a challenging task in this R&D field, especially in industrial applications. The objective of this work is to develop a smart condition monitoring system and a signal processing technique for bearing fault detection. Firstly, a Field Programmable Gate Arrays (FPGA) based sinusoidal generator is developed to generate controllable sinusoidal waveforms and explore FPGA’s potential applications in a data acquisition system to collect vibration signals. Secondly, an adaptive variational mode decomposition (AVMD) technique is proposed for bearing fault detection. The AVMD includes several steps in processing: 1) Signal characteristics are analyzed to determine the signal center frequency and the related parameters. 2) The ensemble-kurtosis index is suggested to select the optimal intrinsic mode function (IMF) to decompose the target signal. 3) The envelope spectrum analysis is performed using the selected IMF to identify the representative features for bearing fault detection. The effectiveness of the proposed AVMD technique is examined by simulation and experimental tests under different bearing conditions, with the comparison of other related bearing fault techniques