Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

Design Techniques for On-Chip Global Signaling Over Lossy Transmission Lines.

This thesis describes techniques for global high-speed signaling over long (~10mm) lossy chip-serial transmission lines. With the increase in clock frequencies to multi-GHz rates, it has become impossible to move data across a die in a single clock cycle using conventional parallel bus-based communication. There are also reliability problems due to timing errors, skew, and jitter in fully synchronous systems. Noise, coupling, and inductive effects become significant for both intermediate length and global routing. A new on-chip lossy transmission line technique is developed and new driver and receiver circuitry for on-chip serial links are described. High-speed long-range serial signaling is best done over transmission lines. However, because of the relatively high sheet resistance of metal interconnect layers, on-chip transmission lines tend to be lossy. Matched termination with resistors and the proper selection of the characteristic impedance of the transmission line structure can effectively suppress ISI. Fast digital CMOS technology allows pulsed mode data drivers to operate at multi-GHz rates. A phase-tuned receiver samples and de-serializes the received signal. Since the sampling instant is tuned to match the received signal eye, there is no requirement to match the clock and signal routing or clock and signal delays. A complete self-testing on-chip transceiver communicating over a 5.8mm on-chip transmission line is implemented in 0.13um CMOS and tested. The measured BER at 9Gbps is less than 10^-10. Interleaving is usually necessary in high serial data rate serializer and de-serializer circuits. Multi-stage LC oscillators can be used to generate low phase noise multi-phases clocks required for interleaving. Conventional coupling between oscillators introduces out of phase currents, and this out of phase current causes a lower effective quality factor for each oscillator stage. However, capacitive coupling, a new technique, introduces in phase coupling between stages. Increased coupling with a ring of capacitors decreases phase spacing error dramatically and, in addition, the phase noise of multi-stages is also decreased thanks to in-phase coupling.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58491/1/parkjy_1.pd

Micropower Impulse Radio For Remote Controlled Insect Flight

Insects have remarkable strength and stamina compared to their body mass and fly and manuver effortlessly in ways that are impossible for present day robotic flyers. Therefore, efforts to control and direct flying insects for our own purposes have a huge potential payoff. One such effort, discussed in this dissertation, concerns the control of a Manduca Sexta moth by sending commands by radio to neural probes implanted in the thorax. The electronics hardware represents a major challenge in itself because the moth can carry only 700 milligrams, most of which is occupied by a small watch-battery. Ultimately, the moth must carry not only a radio receiver to pick up commands sent by the controller, but also a transmitter to return gathered information and fulfill its mission. Commercial "low-power", burst-mode radios have proven inadeqate because the battery cannot satisfy their peak power consumption. Instead, this dissertation focuses on the development of an alternative "impulse radio", which consumes power only during the ~100 picosecond interval required to generate a microwave pulse. The specific transmitter architecture presented here uses a nonlinear transmission line to directly convert digital signals provided by a microcontroller into microwave pulses broadcast by an antenna. This dissertation discusses (1) the background and theory of impulse-radios and (2) nonlinear transmission lines, (3) circuit board prototypes and (4) a CMOS implementation of the trans- mitter, (5) a study of the wireless link between the moth and its controller, as well as (6) efforts to implement the radio using light-weight, inexpensive plastic and polymer materials, before (7) reflecting on the potential of the new transmitter and possible directions for future work

Advanced modelling and design considerations for interconnects in ultra- low power digital system

PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption for advanced System-on- Chip (SoC)s. However, the growing complexity of interconnects behaviour presents a challenge for their adequate modelling, whereby conventional circuit theoretic approaches cannot provide sufficient accuracy. During the last decades, fractional differential calculus has been successfully applied to modelling certain classes of dynamical systems while keeping complexity of the models under acceptable bounds. For example, fractional calculus can help capturing inherent physical effects in electrical networks in a compact form, without following conventional assumptions about linearization of non-linear interconnect components. This thesis tackles the problem of interconnect modelling in its generality to simulate a wide range of interconnection configurations, its capacity to emulate irregular circuit elements and its simplicity in the form of responsible approximation. This includes modelling and analysing interconnections considering their irregular components to add more flexibility and freedom for design. The aim is to achieve the simplest adaptable model with the highest possible accuracy. Thus, the proposed model can be used for fast computer simulation of interconnection behaviour. In addition, this thesis proposes a low power circuit for driving a global interconnect at voltages close to the noise level. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. The major contributions of this thesis are twofold. Firstly, in order to address Ultra-Low Power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumption. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single event upset (SEU)s, which are known to affect DSM circuits working under low voltages. Secondly, the CMOS circuit driving a distributed RLC load has been brought in its analysis into the fractional order domain. This model will make the on-chip interconnect structure easy to adjust by including the effect of fractional orders on the interconnect timing, which has not been considered before. A second-order model for the transfer functions of the proposed general structure is derived, keeping the complexity associated with second-order models for this class of circuits at a minimum. The approach here attaches an important trait of robustness to the circuit design procedure; namely, by simply adjusting the fractional order we can avoid modifying the circuit components. This can also be used to optimise the estimation of the system’s delay for a broad range of frequencies, particularly at the beginning of the design flow, when computational speed is of paramount importance.Iraqi Ministry of Higher Education and Scientific Researc

Cmos Rotary Traveling Wave Oscillators (Rtwos)

Rotary Traveling Wave Oscillator (RTWO) represents a transmission line based technology for multi-gigahertz multiple phase clock generation. RTWO is known for providing low jitter and low phase noise signals but the issue of high power consumption is a major drawback in its application. Direction of wave propagation is random and is determined by the least resistance path in the absence of an external direction control circuit. The objective of this research is to address some of the problems of RTWO design, including high power consumption, uncertainty of propagation direction and optimization of design variables. Included is the modeling of RTWO for sensitivity, phase noise and power analysis. Research objectives were met through design, simulation and implementation. Different designs of RTWO in terms of ring size and number of amplifier stages were implemented and tested. Design tools employed include Agilent ADS, Cadence EDA, SONNET and Altium PCB Designer. Test chip was fabricated using IBM 0.18 μm RF CMOS technology. Performance measures of interest are tuning range, phase noise and power consumption. Agilent ADS and SONNET were used for electromagnetic modeling of transmission lines and electromagnetic field radiation. For each design, electromagnetic simulations were carried out followed by oscillation synthesis based on circuit simulation in Cadence Spectre. RTWO frequencies between 2 GHz and 12 GHz were measured based on the ring size of transmission lines. Simulated microstrip transmission line segments had a quality factor between 5.5 and 18. For the various designs, power consumption ranged from 20 mW to 120 mW. Measured phase noise ranged between -123 dBc/Hz and -87 dBc/Hz at 1 MHz offset. Development also included the design of a wide band buffer and a printed circuit board with high signal integrity for accurate measurement of oscillation frequency and other performance measures. Simulated performance, schematics and measurement results are presented

The MS-processor's register file timing and power evaluation

Power evaluation is an important issue in new proposal chip level architectures due to the big amount of power is dissipated as head and chips have limited head dissipation capacity. The evaluation shown in this technical report don’t use any low-power techniques; main goal of this work is known the upper limit consumption of the Multi-State Processor’s RF design, power optimization is a work to be making through the steps of design flow. Logic design has being performed at transistor level using SPICE simulator, once the basic structures of RF took shape power consumption was analyzed, the source of technology parameters used in this work is Predictive Technology Models (PMT) provided by the Nanoscale Integration and Modeling Group at UC Berkeley [9].Postprint (published version

Investigation of Various Shaping Methods for the Development of a Fully-Monolithic CMOS Constant-Fraction Discriminator

In this work the design of a constant-fraction discriminator (CFD) fabricated in the Orbit Semiconductor l.2-Jl n-well CMOS process is presented. This timing pick-off circuit is designed for use in the readout electronics of the Lead-Scintillator subsystem of the Pioneering High Eenergy Nuclear Ion eXperiment (PHENIX) Electromagnetic Calorimeter at the Relativistic Heavy Ion Collider (RHIC). The design was driven by stringent requirements including low power consumption, small area, arrayable, low cost and a fully integratable shaping network. Various integratable CFD shaping methods are investigated, and the candidate methods chosen for fabrication were the distributed R-C delay-line shaping, lumped-element R-C shaping and Nowlin method shaping. An additional channel of ideal delay-line shaping, utilizing coaxial cable to generate delay, was fabricated and used for a reference in comparing methods. These shaping methods are compared on the basis of die area, time walk performance and timing jitter performance as implemented using the CMOS CFD presented. Each shaping method investigated required no power from the dc supply. Die area for the distributed R-C delay-line, lumped-element R-C, Nowlin method and ideal delay-line (fraction circuit only) were 172 Jl X 70 Jl, 160 Jl X 65 Jl, 179 Jl X 53 Jl and 67 Jl X65Jl,respectively. Timewalkovera100:1dynamicrange(-2Vpeakto-20mVpeak) for these shaping methods in turn was found to be ± 175 ps, ± 150ps , ± 150 ps and ± 185 ps, respectively. Timing jitter performance with a minimum input signal (-20 mVpeak) in rms units for the four methods in turn were 65 ps, 85 ps, 100 ps and 65 ps. The average power dissipated per CFD channel was found to be approximately 12 mW