Augmenting IP blocks for verification and optimization

The verification of digital intellectual property (IP) blocks has always been a challenge. Simple IP blocks with straightforward test inputs, can be quite thoroughly verified with software simulators such as Modelsim. But the verification of a complex System-on-Chip (SoC) on a software simulator can last days or even weeks, and that assumes that every IP on the SoC has a working simulation model. Although modern programmable chips can be monitored in real time with tools like Altera’s Signaltap II, they still only offer monitoring capabilities for a limited amount of signals and for a limited amount of time. To overcome this deficiency, IP information registers (IIR) were developed for this thesis. These registers are used to store information pertaining to the IPs and the SoC as a whole. The information can be static or dynamic, ie. generated before or during run-time . The information itself can be used for many different purposes along with the verification of single IPs or whole SoCs. The case study in this thesis has three parts where three of those purposes are examined with Terasic’s second generation development and education (DE2) board. This physical platform was fitted with two systems, a 2D graphics system embedded with information registers and a system to monitor the first one using these registers. The first part examined the identification aspects with static information whereas the second and third part examined the dynamic aspects of the information registers with their verification and optimization capabilities. Each of these aspects was deemed to offer a good service for developers designing digital circuits

Performance Debugging Frameworks for FPGA High-Level Synthesis

Using high-level synthesis (HLS) tools for field-programmable gate array (FPGA) design is becoming an increasingly popular choice because HLS tools can generate a high-quality design in a short development time. However, current HLS tools still cannot adequately support users in understanding and fixing the performance issues of the current design. That is, current HLS tools lack in performance debugging capability. Previous work on performance debugging automates the process of inserting hardware monitors in low-level register-transfer level (RTL) languages which limits the comprehensibility of the obtained result. Instead, our HLS-based flows offer analysis on a function or loop level and provide more intuitive feedback that can be used to pinpoint the performance bottleneck of a design. In this dissertation, we present a collection of HLS-based debugging frameworks for various purposes and characteristics of the design. First, we address the problem in the HLS synthesis step, where an inaccurate cycle estimation is provided if the program has input-dependent behavior. We propose a new performance estimator that automatically instruments code that models the hardware execution behavior and interprets the information from the HLS software simulation. However, the performance estimation result of this flow may not be accurate for a type of designs that cannot be simulated correctly by existing HLS software simulators. To handle such cases, we propose a new software simulator that provides cycle-accurate result based on the HLS scheduling information. If the input dataset is not available for software simulation or high-level models do not exist for all components of the FPGA design, we also present an on-board monitoring flow for automated cycle extraction and stall analysis. Finally, we address the needs of HLS programmers to automatically find the best set of directives for FPGA designs. We propose a design space exploration (DSE) framework to optimize applications with variable loop bounds in Polybench benchmark. A quantitative comparison among the proposed frameworks is shown using the sparse matrix-vector multiplication benchmark