Optymalizacja sieci FTTH. Telekomunikacja i Techniki Informacyjne, 2014, nr 3-4

Fiber To The Home (FTTH) to najbardziej nowoczesna technologia wśród światłowodowych sieci dostępowych. Podstawowymi wyzwaniami w procesie budowy sieci FTTH są wysoka cena urządzeń i koszt instalacji kabli. Cena urządzeń optycznych wprawdzie stale się obniża, jednak położenie kabla optycznego nadal generuje bardzo duże koszty. W niniejszym artykule przedstawiono problem optymalizacji kosztów instalacji kabla optycznego. Jego rozwiązanie będzie miało praktyczne zastosowanie w projektowaniu sieci FTTH. Ponieważ prezentowany problem jest NP-trudny (Non-deterministic Polynomial-time hard), w celu jego rozwiązania posłużono się algorytmem aproksymacyjnym. Algorytm został zaimplementowany w celu analizy wydajności, która wykazała zadowalającą jakość wyników działania algorytmu z dopuszczalną czasochłonnością. W związku z tym autor proponuje zastosowanie algorytmu w narzędziach do projektowania sieci FTTH

FTTH Network Optimization, Journal of Telecommunications and Information Technology, 2014, nr 4

Fiber To The Home (FTTH) is the most ambitious among optical technologies applied in the access segment of telecommunications networks. The main issues of deploying FTTH are the device price and the installation cost. Whilst the costs of optical devices are gradually decreasing, the cost of optical cable installation remains challenging. In this paper, the problem of optimization that has practical application for FTTH networks is presented. Because the problem is Non-deterministic polynomial-time hard (NP-hard), an approximation algorithm to solve it is proposed. The author has developed the algorithm in a C# program in order to analyze its performance. The analysis confirms that the algorithm gains near-optimal results with acceptable time consumption. Therefore, the algorithm to be applied in a network design tool for FTTH network planning is proposed

Using ant colony optimization for routing in microprocesors

Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities into VLSI devices. Hence it is important to find out ways to utilize these functionalities with optimized power consumption. This work focuses on curbing power consumption at the design stage. This work emphasizes minimizing active power consumption by minimizing the load capacitance of the chip. Capacitance of wires and vias can be minimized using Ant Colony Optimization (ACO) algorithms. ACO provides a multi agent framework for combinatorial optimization problems and hence is used to handle multiple constraints of minimizing wire-length and vias to achieve the goal of minimizing capacitance and hence power consumption. The ACO developed here is able to achieve an 8% reduction of wire-length and 7% reduction in vias thereby providing a 7% reduction in total capacitance, compared to other state of the art routers

Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction

在平面上，考慮障礙物之直角史坦納(Steiner)樹為利用直線或橫線連接所有節點、同時避免穿越障礙物的史坦納樹。在先進的積體電路設計中，繞線的過程必須考慮各種線路、區塊所產生的障礙物，因此這個問題越來越受到重視與關注。除此之外，由於積體電路為多層之製程，這使得在多層繞線平面中，建造考慮障礙物之直角史坦納樹成為一個新的挑戰。然而，考慮障礙物與多層繞線平面大幅增加了問題的難度，所以現存的研究結果都還有進步的空間。在此篇論文中，我們提出一個利用考慮障礙物之連結圖的演算法，它能快速地建造考慮障礙物之直角史坦納樹，而且不同於現存的演算法，我們的演算法在節點數為二以及其他許多情況達到最佳解。而對於在多層繞線平面中的問題，我們也提出許多不同於單層繞線平面的性質，並且適當地延伸單層繞線的演算法來解決此問題。實驗結果顯示，比起當今先進的演算法，我們的演算法能產生線長更短的考慮障礙物之直角史坦納樹。Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins by vertical/horizontal edges, possibly through some additional points (called Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Besides, because modern nanometer IC designs are processed layer by layer, it is a new challenge for designers to deal with the multi-layer OARSMT (ML-OARSMT) problem where pins are connected by vertical/horizontal edges within layers and vias between layers. Nevertheless, the presences of obstacles and multi-layers significantly increase the problem complexity, and thus most previous works for the OARSMT problem on a layer suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph (OASG), this thesis presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction on a layer. Unlike previous heuristics, our algorithm guarantees to find an optimal solution for any 2-pin net and many higher-pin nets. Furthermore, we identify key different properties of the ML-OARSMT problem from the single-layer counterpart and present the first algorithm to solve the ML-OARSMT problem. This algorithm can also guarantee an optimal solution for any 2-pin net and many higher-pin nets. Extensive experiments show that our algorithms result in significantly shorter wirelengths than all state-of-the-art works.Acknowledgements i Abstract (Chinese) ii Abstract iii List of Tables vii List of Figures viii Chapter 1. Introduction 1 1.1 Obstacle-Avoiding Rectilinear Routing ............. 1 1.2 Previous Work ..................................... 3 1.2.1 Maze-Routing Based Approach .................... 3 1.2.2 Nondeterministic Approach ...................... 4 1.2.3 Construction-by-Correction Approach ............ 5 1.2.4 Connection-Graph Based Approach ................ 6 1.2.5 Hybrid Approach ................................ 9 1.3 Contributions ..................................... 9 1.4 Thesis Organization ............................... 11 Chapter 2. Problem Formulations 12 Chapter 3. Algorithm 15 3.1 OASG Construction ................................. 16 3.1.1 OASG Construction within a Region .............. 19 3.1.2 Properties of Pin-Vertex Shortest Paths ........ 22 3.2 OAST Construction ................................. 24 3.2.1 Pin-Vertices Shortest Path Computation ......... 24 3.2.2 Initial OAST Construction ...................... 25 3.2.3 Local Refinement ............................... 25 3.3 OARST Construction ................................ 26 3.4 OARSMT Construction ............................... 29 3.4.1 Overlapping Edge Removal ....................... 29 3.4.2 Redundant Vertex Removal ....................... 31 3.4.3 U-Shaped Pattern Refinement .................... 31 3.5 Optimality ........................................ 33 3.6 Complexity Analysis ............................... 35 3.6.1 Number of Edges in the OASG .................... 35 3.6.2 Time Complexity ................................ 39 Chapter 4. Extension to the ML-OARSMT Problem 41 4.1 ML-OASG Construction .............................. 43 4.1.1 Vertex Projection between Layers ............... 47 4.1.2 Vertex Projection within a Layer ............... 49 4.1.3 ML-OASG Construction ........................... 50 4.2 ML-OAST Construction .............................. 53 4.3 ML-OARST Construction ............................. 54 4.4 ML-OARSMT Construction ............................ 54 4.5 Optimality ........................................ 55 4.6 Complexity Analysis ............................... 56 Chapter 5. Experimental Results 57 5.1 The OARSMT problem ................................ 57 5.2 The ML-OARSMT problem ............................. 61 Chapter 6. Conclusions 67 Bibliography 6

Efficient obstacle-avoiding rectilinear Steiner tree construction

Abstract—Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works. Index Terms—Physical design, routing, spanning tree, Steiner tree. I

Obstacle-avoiding rectilinear Steiner tree.

Li, Liang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references (leaves 57-61).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Partitioning --- p.1Chapter 1.1.2 --- Floorplanning and Placement --- p.2Chapter 1.1.3 --- Routing --- p.2Chapter 1.1.4 --- Compaction --- p.3Chapter 1.2 --- Motivations --- p.3Chapter 1.3 --- Problem Formulation --- p.4Chapter 1.3.1 --- Properties of OARSMT --- p.4Chapter 1.4 --- Progress on the Problem --- p.4Chapter 1.5 --- Contributions --- p.5Chapter 1.6 --- Thesis Organization --- p.6Chapter 2 --- Literature Review on OARSMT --- p.8Chapter 2.1 --- Introduction --- p.8Chapter 2.2 --- Previous Methods --- p.9Chapter 2.2.1 --- OARSMT --- p.9Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14Chapter 2.3 --- Comparison --- p.15Chapter 3 --- Heuristic Method --- p.17Chapter 3.1 --- Introduction --- p.17Chapter 3.2 --- Our Approach --- p.18Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18Chapter 3.2.2 --- Propagation --- p.20Chapter 3.2.3 --- Backtrack --- p.23Chapter 3.2.4 --- Finding MST --- p.26Chapter 3.2.5 --- Local Refinement Scheme --- p.26Chapter 3.3 --- Experimental Results --- p.28Chapter 3.4 --- Summary --- p.28Chapter 4 --- Exact Method --- p.32Chapter 4.1 --- Introduction --- p.32Chapter 4.2 --- Review on GeoSteiner --- p.33Chapter 4.3 --- Overview of our Approach --- p.33Chapter 4.4 --- FST with Virtual Pins --- p.34Chapter 4.4.1 --- Definition of FST --- p.34Chapter 4.4.2 --- Notations --- p.36Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50Chapter 4.7 --- Experimental Results --- p.52Chapter 4.8 --- Summary --- p.53Chapter 5 --- Conclusion --- p.55Bibliography --- p.6

Telekomunikacja i Techniki Informacyjne, 2014, nr 3-4

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Shortest Paths and Steiner Trees in VLSI Routing

Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer

Journal of Telecommunications and Information Technology, 2014, nr 4

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