On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods

No abstract availabl

FIR Filter Implementation by Efficient Sharing of Horizontal and Vertical Common Sub-expressions

No abstract availabl

Towards an optimised VLSI design algorithm for the constant matrix multiplication problem

The efficient design of multiplierless implementations of constant matrix multipliers is challenged by the huge solution search spaces even for small scale problems. Previous approaches tend to use hill-climbing algorithms risking sub-optimal results. The proposed algorithm avoids this by exploring parallel solutions. The computational complexity is tackled by modelling the problem in a format amenable to genetic programming and hardware acceleration. Results show an improvement on state of the art algorithms with future potential for even greater savings

RECONFIGURABLE LOW POWER AND AREA EFFICIENT ESPFFIR FILTER USING VHBCSE MULTIPLIER

Reconfigurable Even Symmetric Parallel Fast Finite Impulse Response (RESPFFIR) filter shall be utilized as the Processing Element (PE) in Software Defined Radio (SDR) design to improve the throughput. The number of multipliers required in RESPFFIR filter increases when parallelism length increases. The Constant Multiplier (CM) technique is used to diminish the power consumption in FIR filters by reducing the number of Logical Operators (LO) and Logical Depth (LD). Binary Common Subexpression Elimination (BCSE) method is suitable to exploit symmetric coefficient in FIR filters. The Vertical Horizontal Binary Common Subexpression Elimination (VHBCSE) technique based Constant Multiplier (CM) design further diminish the number of LO and LD. The 2-bit BCSE algorithm has been applied vertically across neighboring coefficients and HCSE makes use of CSs that arise within each coefficient to eradicate redundant computations, which intern reduce logical operator in constant multiplier. This paper presents the design of Reconfigurable Even Symmetric Parallel Fast Finite Impulse Response (RESPFFIR) filter using VHBCSE based CM multiplier, which is reconfigurable with reduced power and area consumption without degrading the throughput. The power consumption reduces by 12% and the area required gets reduced by 24% in the proposed design when compared with existing CSE Hcub-n Multiple Constant Multiplier based  ESPFFIR filter design. The analysis is done using Cadence RC synthesize tools

Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression

International audienceThe Discrete Cosine Transform (DCT)-based image com- pression is widely used in today's communication systems. Signi cant research devoted to this domain has demonstrated that the optical com- pression methods can o er a higher speed but su er from bad image quality and a growing complexity. To meet the challenges of higher im- age quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI archi- tecture of the DCT algorithm and an e cient quantization technique. Our approach is, rstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a recon gurable quantization method is presented to e ectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and com- parisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement

Synthesis of reconfigurable multiplier blocks: part I: fundamentals

Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time multiplexed implementation of multiple constant multiplications. This paper and its companion paper (subtitled Part II- Algorithm) together present a systematic synthesis method for Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) ReMB designs. This paper presents the necessary foundation and terminology needed for developing a systematic synthesis technique. The companion paper illustrates the synthesis method through examples. The method proposed achieves reduced logic-depth and area over standard multipliers / multiplier blocks

An efficient design or fractional-delay digital FIR filters using the Farrow structure

Fractional-delay digital filter (FD-DF), implemented using the Farrow (1988) structure, is very attractive in providing online tuning delay of digital signals. This paper proposes a new method for the design of such Farrow-based FD-DF using sum-of-powers-of-two (SOPOT) coefficients. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Design examples show that the proposed method can greatly reduce the design time and complexity of the Farrow structure while providing comparable phase and amplitude responses.published_or_final_versio

On the design and efficient implementation of the Farrow structure

This letter proposes an efficient implementation of the Farrow structure using sum-of-powers-of-two (SOPOT) coefficients and multiplier-block (MB). In particular, a novel algorithm for designing the Farrow coefficients in SOPOT form is detailed. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Using MB, the redundancy between multipliers can be fully exploited through the reuse of the intermediate results generated. Design examples show that the proposed method can greatly reduce the complexity of the Farrow structure while providing comparable phase and amplitude responses.published_or_final_versio