Performance modeling of embedded applications with zero architectural knowledge

Performance estimation is a key step in the development of an embedded system. Normally, the performance evaluation is performed using a simulator or a performance mathematical model of the target architecture. However, both these approaches are usually based on the knowledge of the architectural details of the target. In this paper we present a methodology for automatically building an analytical model to estimate the performance of an application on a generic processor without requiring any information about the processor architecture but the one provided by the GNU GCC Intermediate Representation. The proposed methodology exploits the linear regression technique based on an application analysis performed on the Register Transfer Level internal representation of the GNU GCC compiler. The benefits of working with this type of model and with this intermediate representation are three: we take into account most of the compiler optimizations, we implicitly consider some architectural characteristics of the target processor and we can easily estimate the performance of portions of the specification. We validate our approach by evaluating with cross-validation technique the accuracy and the generality of the performance models built for the ARM926EJ-S and the LEON3 processor

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

The current many-core architectures are generally evaluated by a detailed emulation with a cycle-accurate simulation of the execution time. However this detailed simulation of the architecture makes the evaluation of large programs very slow. Since the focus in many-core architecture is shifting from the performance of the individual core to the overall behavior of chip, high-level simulations are becoming neces- sary, which evaluate the same architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions. We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many fine- grained multi-threaded cores. This simulator allows us to investigate mapping and scheduling strategies of families (i.e. groups of threads) in developing an operating environ- ment for the Microgrid. The previous method to evaluate the workload counted in basic blocks was inaccurate. The key problem is that with many concurrent threads the la- tency of certain instructions are hidden because of the multi- threaded nature of the core. This paper presents a technique to manage the execution time of different types of instruc- tions with thread concurrency. We believe to achieve high accuracy in evaluating programs in the high-level simulator

Apport de la co-simulation dans la conception de l'architecture des dispositifs de commande numérique pour les systèmes électriques

Ce travail est issu d'un constat concernant l'Adéquation entre les contraintes associées aux Algorithmes de commande et l'Architecture d'un dispositif de commande numérique (A3). En effet, les contraintes temporelles et fonctionnelles de ces algorithmes se répercutent sur les choix architecturaux du dispositif. La répartition des tâches entre les parties "câblées" (composants logiques programmables) et les parties "programmées" (utilisation de microprocesseurs) ne peut plus se faire à priori étant donné les évolutions technologiques dans le domaine des composants numériques. La première partie de ce mémoire est consacrée à la présentation et à l'analyse des tâches potentielles d'un dispositif de commande dédié aux systèmes électriques avec leurs contraintes fonctionnelles et temporelles. Dans un second temps, une synthèse sur le co-design, thème de recherche dans le domaine de l'électronique numérique, est développée afin de présenter différentes voies de recherche sur les outils d'aide à la conception des dispositifs de commande. Dans la deuxième partie, un outil potentiel, nommé "co-simulation", est étudié afin d'en déterminer l'intérêt et les limites. Les différentes composantes nécessaires à la mise en place d'un environnement de co-simulation sont présentées et développées au travers d'exemples d'applications. Une partie de l'environnement de co-simulation est ensuite exploitée dans la troisième section afin d'étudier différentes solutions pour l'implantation d'observateurs dédiés aux convertisseurs multicellulaires séries. Des résultats expérimentaux concernant l'implantation d'un émulateur temps réel du convertisseur viennent enfin confirmer la validité de l'environnement de co-simulation que nous avons réalisé. La dernière partie est réservée à la synthèse du travail ainsi qu'aux conclusions et perspectives. ABSTRACT : This work results from a report about the lack of adequacy between the constraints of the control algorithms and the architecture of a control device. The timing and functional constraints of an algorithm has some consequences in the architectural choices of the control device. According to the technological progress in the electronic components, we cannot make the tasks distribution between the hardware part and the software part any more without particular analysis. The first part is dedicated to the introduction and the analysis of the main potential tasks which can be implanted on a control device for the electrical systems with their timing and functional constraints. Then, a synthesis about co-design which is a subject of research in the electronic domain is made. This synthesis introduces various ways of research on tools of aided to the design of control devices. In a second part, one of a possible tool is studied in order to show the interest and its limits. The different components used to build a co-simulation environment are presented and developed with some examples. In a third part, co-simulation elements are used to study various solutions on the implantation of particular observers. These observers are dedicated to a four level multicell converter. Some experimental results about an emulator of the multicell converter (which is a part of the observers) are shown and allow to validate the co-simulation environment built. The last part is dedicated to the synthesis of the work and to the conclusions and perspectives

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

The limitations of clock frequency and power dissipation of deep sub-micron CMOS technology have led to the development of massively parallel computing platforms. They consist of dozens or hundreds of processing units and offer a high degree of parallelism. Taking advantage of that parallelism and transforming it into high program performances requires the usage of appropriate parallel programming models and paradigms. Currently, a common practice is to develop parallel applications using methods evolving directly from sequential programming models. However, they lack the abstractions to properly express the concurrency of the processes. An alternative approach is to implement dataflow applications, where the algorithms are described in terms of streams and operators thus their parallelism is directly exposed. Since algorithms are described in an abstract way, they can be easily ported to different types of platforms. Several dataflow models of computation (MoCs) have been formalized so far. They differ in terms of their expressiveness (ability to handle dynamic behavior) and complexity of analysis. So far, most of the research efforts have focused on the simpler cases of static dataflow MoCs, where many analyses are possible at compile-time and several optimization problems are greatly simplified. At the same time, for the most expressive and the most difficult to analyze dynamic dataflow (DDF), there is still a dearth of tools supporting a systematic and automated analysis minimizing the programming efforts of the designer. The objective of this Thesis is to provide a complete framework to analyze, evaluate and refactor DDF applications expressed using the RVC-CAL language. The methodology relies on a systematic design space exploration (DSE) examining different design alternatives in order to optimize the chosen objective function while satisfying the constraints. The research contributions start from a rigorous DSE problem formulation. This provides a basis for the definition of a complete and novel analysis methodology enabling systematic performance improvements of DDF applications. Different stages of the methodology include exploration heuristics, performance estimation and identification of refactoring directions. All of the stages are implemented as appropriate software tools. The contributions are substantiated by several experiments performed with complex dynamic applications on different types of physical platforms