The Impact of LSI (Large Scale Integration) on System Packaging

System packaging of LSI circuit

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

MICROSTRUCTURAL CHARACTERIZATION AND THERMAL CYCLING RELIABILITY OF SOLDERS UNDER ISOTHERMAL AGING AND ELECTRICAL CURRENT

Solder joints on printed circuit boards provide electrical and mechanical connections between electronic devices and metallized patterns on boards. These solder joints are often the cause of failure in electronic packages. Solders age under storage and operational life conditions, which can include temperature, mechanical loads, and electrical current. Aging occurring at a constant temperature is called isothermal aging. Isothermal aging leads to coarsening of the bulk microstructure and increased interfacial intermetallic compounds at the solder-pad interface. The coarsening of the solder bulk degrades the creep properties of solders, whereas the voiding and brittleness of interfacial intermetallic compounds leads to mechanical weakness of the solder joint. Industry guidelines on solder interconnect reliability test methods recommend preconditioning the solder assemblies by isothermal aging before conducting reliability tests. The guidelines assume that isothermal aging simulates a "reasonable use period," but do not relate the isothermal aging levels with specific use conditions. Studies on the effect of isothermal aging on the thermal cycling reliability of tin-lead and tin-silver-copper solders are limited in scope, and results have been contradictory. The effect of electrical current on solder joints has been has mostly focused on current densities above 104A/cm2 with high ambient temperature (≥100oC), where electromigration, thermomigration, and Joule heating are the dominant failure mechanisms. The effect of current density below 104A/cm2 on temperature cycling fatigue of solders has not been established. This research provides the relation between isothermal aging and the thermal cycling reliability of select Sn-based solders. The Sn-based solders with 3%, 1%, and 0% silver content that have replaced tin-lead are studied and compared against tin-lead solder. The activation energy and growth exponents of the Arrhenius model for the intermetallic growth in the solders are provided. An aging metric to quantify the aging of solder joints, in terms of phase size in the solder bulk and interfacial intermetallic compound thickness at the solder-pad interface, is established. Based on the findings of thermal cycling tests on aged solder assemblies, recommendations are made for isothermal aging of solders before thermal cycling tests. Additionally, the effect of active electrical current at 103 A/cm2 on thermal cycling reliability is reported

MODELING RATE DEPENDENT DURABILITY OF LOW-Ag SAC INTERCONNECTS FOR AREA ARRAY PACKAGES UNDER TORSION LOADS

The thesis discusses modeling rate-dependent durability of solder interconnects under mechanical torsion loading for surface mount area array components. The study discusses an approach to incorporate strain-rate dependency in durability estimation for solder interconnects. The components under study are two configurations of BGAs (ball grid array) assembled with select lead-free solders. A torsion test setup is used to apply displacement controlled loads on the test board. Accelerated test load profile is experimentally determined. Torsion test is carried out for all the components under investigation to failure. Strain-rate dependent (Johnson-Cook model) and strain-rate independent, elastic-plastic properties are used to model the solders in finite element simulation. Damage model from literature is used to estimate the durability for SAC305 solder to validate the approach. Test data is used to extract damage model constants for SAC105 solder and extract mechanical fatigue durability curve

COMPARISON OF INTERCONNECT FAILURES OF ELECTRONIC COMPONENTS MOUNTED ON FR-4 BOARDS WITH SN37PB AND SN3.0AG0.5CU SOLDERS UNDER RAPID LOADING CONDITIONS.

Electronic circuit boards can experience rapid loading through shock or vibration events during their lives; these events can happen in transportation, manufacture, or in field conditions. Due to the lead-free migration, it is necessary to evaluate how this rapid loading affects the durability of a leading lead free solder alternative (Sn3.0Ag0.5Cu) assemblies as compared with traditional eutectic lead based solder Sn37Pb assemblies. A literature review showed that there is little agreement on the fatigue behavior of Sn37Pb solder assemblies and Sn3.0Ag0.5Cu solder assemblies subjected to rapid loading. To evaluate the failure behavior of Sn37Pb and Sn3.0Ag0.5Cu solder assemblies under rapid loading conditions, leadless chip resistors (LCR), ball grid arrays (BGA), small outline integrated circuits (SOIC), and small outline transistors (SOT) were subjected to four point bend tests via a servo-hydraulic testing machine at printed wiring board (PWB) strain rates greater than 0.1/s. The PWB strain was the metric used to evaluate the failures. The PBGAs and LCRs were examined with both Sn37Pb and Sn3.0Ag0.5Cu solders. There was no significant difference found in the resulting test data for the behavior of the two solder assembly types in the high cycle fatigue regime. PBGA assemblies with both solders were also evaluated at a higher strain rate, approximately 1/s, using drop testing. There was no discernable difference found between the assemblies as well as no difference in the failure rate of the PBGAs at this higher strain rate. The PWB strain was converted to an equivalent solder stress index using finite element analysis. This equivalent stress index value was used to compare the results from the LCR and BGA testing for Sn37Pb and Sn3.0Ag0.5Cu. Independently generated BGA data that differed with respect to many testing variables was adjusted and incorporated to this comparison. The resulting plot did not show any significant differences between the behaviors of the two solder assemblies under rapid loading outside of the ultra low cycle fatigue regime, where the assemblies with Sn37Pb solder outperformed the assemblies with SnAgCu solder

Optimization for finite element modeling of electronic components under dynamic loaDing

Usage of electronic components in the U.S. ARMY applications is becoming more challenging due to their usage in harsh environments. Experimental verification of these components is expensive and it can yield information about specific locations only. This research outlines the finite element modeling methodology for these electronic components that are subjected to high acceleration loads that occur over extremely short time such as impact, gun firing and blast events. Due to their miniature size these finite element models are computationally expensive. An optimization engine was presented to have an efficient analysis procedure that provides a combination of accuracy, computational speed and modeling simplicity. This research also involves experimental testing of the electronic components mounted on the circuit boards. Testing was conducted at different strain levels in order to study the behavior of boards. Finite element models were developed for these tests and compared with experimental results

Modeling the SAC microstructure evolution under thermal, thermomechanical and electrical constraints

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HIGH ACCELERATIONS PRODUCED THROUGH SECONDARY IMPACT AND ITS EFFECT ON RELIABILITY OF PRINTED WIRING ASSEMBLIES

The focus of this thesis is the investigation of extremely high accelerations through secondary impact and its effect on reliability of printed wiring assemblies. The test equipment consists of a commercially available drop system and a commercially available attachment termed a Dual Mass Shock Amplifier (DMSA), which extends the impact acceleration range to as much as 30,000 Gs by utilizing secondary impact dynamics. Further secondary impacts between the test vehicle and fixture are intentionally generated in simulation and tested experimentally to imitate board 'slap' phenomena in product assemblies, and to generate even further amplification of the acceleration at various locations on the test specimen. In this thesis a detailed description of the test equipment and modeling techniques are provided. Model complexity ranges from simple analytic closed-form rigid-body mechanics to detailed nonlinear dynamic finite element analysis. The effects of different equipment design parameters (table mass, spring stiffness, table clearance) are investigated through parametric modeling. The effects of contact parameters (constraint enforcement algorithms, stiffness, damping) on model accuracy are explored. Test fixtures for high shock accelerations are discussed and used for board level reliability testing of printed wire assemblies containing WLCSP49s and MEMS microphones

Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices