Physics and Technology of Silicon Carbide Devices

Recently, some SiC power devices such as Schottky-barrier diodes (SBDs), metal-oxide-semiconductor field-effect-transistors (MOSFETs), junction FETs (JFETs), and their integrated modules have come onto the market. However, to stably supply them and reduce their cost, further improvements for material characterizations and those for device processing are still necessary. This book abundantly describes recent technologies on manufacturing, processing, characterization, modeling, and so on for SiC devices. In particular, for explanation of technologies, I was always careful to argue physics underlying the technologies as much as possible. If this book could be a little helpful to progress of SiC devices, it will be my unexpected happiness

Characterisation of silicon carbide CMOS devices for high temperature applications

PhD ThesisIn recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.Engineering and Physical Sciences Research Council (EPSRC) and Raytheon U

Feature Papers in Electronic Materials Section

This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book

Surface engineering for silicon carbide interface

PhD ThesisSilicon carbide technology has made a significant improvements in these recent years, with a range of different devices, such as diodes, junction field effect transistors (JFETs) and metaloxide-semiconductor field effect transistors (MOSFETs) becoming commercially viable. The availability of relatively large and high quality wafers of 4H-SiC for device development has facilitated exciting breakthroughs throughout the world. The application areas of 4H-SiC devices include extreme environments such as high power, high frequency, high temperatures as well as optoelectronics. SiC technology has became indispensable due to the increasing demands from industrial sectors including automotive, military and aerospace. One of the crucial challenges for 4H-SiC MOSFETs is to increase the channel mobility which is plagued by the high density of interface traps. Post oxidation annealing (POA) in nitrogen gas environment or nitridation has become a standard process for the fabrication of MOSFETs with acceptable channel mobility around 35 cm2 /Vs, only about 4 % of the bulk mobility. POA using phosphoryl chloride (POCl3) or phosphorus pentoxide (P2O5) sources converts SiO2 into phospho-silicate glass (PSG) and has succesfully improved the channel mobility by a factor of 3 in comparison to nitridation. However, PSG is a polar material that increases the instability of MOS devices characteristic especially at high temperatures. In this work, the effect of inclusion of phosphorus (at an atomic concentration below 1 %) on the high temperature characteristics (up to 300◦C) of the SiO2/SiC interface is investigated. Capacitance – voltage measurements taken over a range of frequencies have been utilized to extract parameters including flatband voltage, threshold voltage, effective oxide charge, and interface state density. The variation of these parameters with temperature has been investigated for bias sweeps in opposing directions and a comparison made between phosphorus doped and undoped oxides. At room temperature, the effective oxide charge for SiO2 may be reduced by the phosphorus termination of dangling bonds at the interface. However, at high temperatures, the effective charge in the phosphorus doped oxide remains unstable and effects such as flatband voltage shift and threshold voltage shift dominate the characteristics. The instability in these characteristics was found to result from the trapped charges in the oxide (±1012 cm−3 ) or near interface traps at the interface of the gate oxide and the semiconductor (1012 to 1013cm−2 eV−1 ). Hence, the performance enhancements observed for phosphorus doped oxides are not realised in devices operated at elevated temperatures. v The electrical characteristics of 4H-SiC CMOS capacitor and transistor structures have been compared to the recently developed inversion MOS capacitor structure. Parameters including the interface state density, flatband voltage, threshold voltage and effective charge have been acquired from C-V characteristics of MOS capacitors to assess the effectiveness of the fabrication process in realising high quality gate dielectrics for CMOS process. A maximum critical electric field, in excess of 9.5 MV/cm has been demonstrated by the MOS capacitors without sustaining any oxide breakdown. Whilst, the interface trap density extracted from the n-type MOS capacitor is strongly correlated with n-channel field effect mobility, the channel mobility in the p-channel data shows no correlation. The impact of elevated temperatures on device characteristics of MOS capacitors and MOSFETs were also investigated utilizing C-V and I-V measurements performed at temperatures up to 400 ◦C. The temperature dependence of the flatband voltage, effective oxide charge and interface state density for MOS capacitors and the field effect mobility, threshold voltage and substhreshold swing for MOSFETs was examined in this section to study the effect of different dielectric formation at elevated temperatures. Finally, for the first time, the characteristics of inversion MOS capacitors with different frequencies (10 kHz to 1 MHz) for n and p-type are reported. The correlation between inversion capacitance and field effect mobility at room and elevated temperatures are discussed as a new method to assess the quality of SiC/SiO2 interface. For the first time, the characteristics of 3D structures formed in silicon carbide for the realisation of ultra-high performance nanoscale transistors, based on the FinFET topology is investigated. C-V characteristics show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices. Two distinct peaks in the conductance – voltage characteristics are observed, centered at the flatband voltages, where the peak located at high bias correlates with the behaviour of the sidewall area. This suggests that the chemical behaviour of the sidewalls differs from those of the (0001) wafer surface. The breakdown electric field of the dielectric film grown on the 3D structure is in excess of 3 MVcm−1 . It is demonstrated that 3D transistors (FinFETs) do not utilise the gate voltage range where the abnormal characteristics exist and so this work reports for the first time the possibility of high performance nanoscale transistors in silicon carbide that can operate at high temperatures.Universiti Teknikal Malaysia Melaka and the the Ministry of Higher Education (MOHE) for sponsoring my study through the SLAB scholarship

Investigation of SiC/Oxide Interface Structures by Spectroscopic Ellipsometry

We have investigated SiC/oxide interface structures by the use of spectroscopic ellipsometry. The depth profile of the optical constants of thermally grown oxide layers on SiC was obtained by observing the slope-shaped oxide layers, and the results suggest the existence of the interface layers, around 1 nm in thickness, having high refractive index than those of both SiC and SiO2. The wavelength dispersions of optical constants of the interface layers were measured in the range of visible to deep UV spectral region, and we found the interface layers have similar dispersion to that of SiC, though the refractive indices are around 1 larger than SiC, which suggests the interface layers are neither transition layers nor roughness layers, but modified SiC, e.g., strained and/or modified composition. By the use of an in-situ ellipsometer, real-time observation of SiC oxidation was performed, and the growth rate enhancement was found in the thin thickness regime as in the case of Si oxidation, which cannot be explained by the Deal-Grove model proposed for Si oxidation. From the measurements of the oxidation temperature and oxygen partial pressure dependences of oxidation rate in the initial stage of oxidation, we have discussed the interface structures and their formation mechanisms within the framework of the interfacial Si-C emission model we proposed for SiC oxidation mechanism

Electronic Structure of SiC/SiO2 by Density Functional Theory

Silicon carbide (SiC) is a promising semiconductor material with desirable properties for many applications. SiC-based electronic devices and circuits are being developed for use in high-temperature, high-power, and high-radiation conditions under which conventional semiconductors cannot function. Additionally, it has the advantage of growing a native oxide, SiO2, by simple thermal oxidation. Despite all desirable properties, SiC-based devices still face major challenges. The main problem of SiC-based devices is the great density of imperfections at the SiC/SiO2 interface, which not only degrades the device performance but also causes reliability problems coming from the extreme operating conditions. The quality of the interface affects the channel mobility of MOSFETs, which is the most critical parameter of devices. In this work a hybrid functional density functional theory framework is employed to model the (0001)4H-SiC/SiO2 abrupt interface. Using this, defect energy levels in the bandgap have been calculated through the total and projected density of states. There is experimental evidence for improvement of the quality of the interface after passivation, However the atomic mechanisms of the improvement are not yet clear., Thus, the impact of various passivations on the potential defects has also been studied. Since the interface of SiC/SiO2 is not perfectly abrupt, several atomic configurations for (0001)4H-SiC/SiO2 transition layers have also been modeled, and their effect on the bandgap, and the near interface trap density has been studied. A DFT-based Monte Carlo carrier transport simulation technique is employed to compute the average velocities, phonon-limited and ionized-impurity-limited mobilities of the most probable transition layer structures. Finally, since low frequency noise calculation is a powerful tool to diagnose quality and reliability of semiconductor devices, a DFT-based method is presented to calculate the current spectral noise density of the (0001)4H-SiC/SiO2 transition layers

4H-SiC metal oxide semiconductor devices

PhD ThesisMetal oxide semiconductor (MOS) devices are the most important component in advanced integrated circuits (ICs). The success of Si in CMOS technology is owing to the excellent interface formed between Si and SiO2. However, Si-based electronic devices are not suitable to operate in high power, high frequency and high temperature conditions due to material limitations. 4H-SiC with a wide bandgap, high critical electric field, high thermal conductivity and high saturation drift velocity, is an attractive semiconductor material for extreme conditions. However, high quality oxide-semiconductor interfaces are still a major challenge in 4H-SiC MOS devices. This thesis focuses on interface studies of 4H-SiC MOS devices. The main aim is to produce high quality oxide/4H-SiC interfaces by the introduction of an ultrathin SiO2 layer between deposited oxides and 4H-SiC. Ultrathin SiO2 layers can be grown on 4H-SiC using a low thermal budget technique followed by Al2O3 deposition using ALD. N-type and p-type MOS capacitors were fabricated using a gate oxidation of 600 °C for 3 min, which produced SiO2 of thickness 0.7 nm as estimated using ARXPS. Electrical characterisation demonstrates an interface trap density (Dit) of 4-6 × 1011 cm-2eV-1 at 0.2 eV from the conduction and valence band edges. This represents a reduction in Dit by 1-2 orders of magnitude compared to the devices fabricated at 1150 °C for 180 min in the furnace. Furthermore, field effect channel mobility as high as 125 cm2/V.s and a subthreshold slope of 130 mV/dec were obtained from MOSFETs using similar gate stacks. The mobility of MOSFETs decreases with increasing temperature indicating that the electron conductivity is limited by phonon scattering rather than Coulomb scattering, and proves that Dit at the oxide/4H-SiC has been reduced. The ultrathin layer is believed to be a good interface layer between Al2O3 and 4H-SiC. As the temperature and time of the oxidation process increased, resulting in thicker SiO2, the values of Dit increased for both p-type and n-type MOS capacitors. Ultrathin SiO2 layers were also grown underneath a deposited SiO2 layer by N2O annealing at 1175 °C. From n-type MOS capacitor results, the lowest values of Dit obtained were 1.7 × 1012 cm-2eV-1 at 0.2 eV below the conduction band edge, for gate oxides consisting of 60 nm deposited SiO2 followed by 90 min of N2O annealing. This process produced a SiO2 layer 0.68 nm thick, estimated using the Deal-Grove model. The values of Dit increased as the grown SiO2 thicknesses became thicker or thinner than 0.68 nm. This trend is similar to what ii was found in ultrathin SiO2/Al2O3 gate stacks of MOS capacitors proving that 0.7 nm thick is the best thickness of SiO2 to use for 4H-SiC MOS devices. Electrical measurement up to 300 °C proved that these fabricated MOS devices are able to operate well at high temperature. MOSFETs utilizing ultrathin SiO2/Al2O3 gate stacks could retain their enhancement mode behaviour even at high temperature demonstrating the devices capability to be operated in extreme conditions. Both gate stacks also exhibited a low leakage current and were able to withstand electric fields far above 3 MV/cm, which is needed for actual operating system. The scope of these findings points to solutions for the interface challenges in 4H-SiC MOS devices. A thermally grown SiO2 layer 0.7 nm thick exhibited the lowest Dit values for both gate stacks and also produced high field effect channel mobility in MOSFETs. It is anticipated that this fabrication approach will mitigate the oxide/4H-SiC interface problem and contribute towards the development of improved power electronic devices.Ministry of Education Malaysia (MOHE) and in part by the Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka for financially sponsored my study through SLAI scholarship. Special thanks to Engineering and Physical Sciences Research Council (EPSRC), UK for providing the financial support to carry out this research

CVD-Wachstum von (001) und (111) 3C-SiC Epi-Schichten und ihre Grenzflächenreaktivität mit dielektrischen Praseodymiumoxidschichten

In this work, growth and characterisation of 3C-SiC thin films, investigation of oxidation of thus prepared layers and Pr-silicate and AlON based interface with SiC have been studied. Chemical vapor deposition of 3C-SiC thin films on Si(001) and Si(111) substrates has been investigated. Prior to the actual SiC growth, preparation of initial buffer layers of SiC was done. Using such a buffer layer, epitaxial growth of 3C-SiC has been achieved on Si(111) and Si(001) substrates. The temperature of 1100°C and 1150°C has been determined to be the optimal temperature for 3C-SiC growth on Si (111) and Si(001) substrates respectively. The oxidation studies on SiC revealed that a slow oxidation process at moderate temperatures in steps was useful in reducing and suppressing the g-C at the SiO2/SiC interface. Clean, graphitefree SiO2 has been successfully grown on 3C-SiC by silicon evaporation and UHV anneal. For the application of high-k Pr2O3 on silicon carbide, plausible interlayer, Pr-Silicate and AlON, have been investigated. Praseodymium silicate has been prepared successfully completely consuming the SiO2 and simultaneously suppressing the graphitic carbon formation. A comparatively more stable interlayer using AlON has been achieved. This interlayer mainly consists of stable phases of AlN along with some amount of Pr-aluminates and CN. Such layers act as a reaction barrier between Pr2O3 and SiC, and simultaneously provide higher band offsets.Im Rahmen dieser Arbeit wird das Wachstum und die Charakterisierung von 3C-SiC Filmen, deren Oxidation, sowie das darauf präparierte Pr-Silikat und die AlON abgeleitete Grenzfläche untersucht. Dünne 3C-SiC Filme wurden auf Si(001) und Si(111) Oberflächen mit Hilfe von Chemical Vapor Deposition Verfahren hergestellt. Vor dem eigentlichen SiC-Wachstum wurde eine SiC Zwischenschicht präpariert. Durch diese Buffer-Schicht wurde das epitaktische Wachstum von 3C-SiC auf Si(111) und Si(001) erst ermöglicht. Als optimale Präparationstemperaturen für 3C-SiC auf Si(111) und Si(001) konnten 1100°C und 1150°C gefunden werden. Im Verlaufe der Oxidation hat sich ein langsamer Stufenprozess mit moderaten Temperaturen als hilfreich erwiesen, um die Graphitisierung an der SiO2/SiC Grenzfläche zu minimieren. Sauberes, graphitfreies SiO2 konnte somit auf 3C-SiC mit Hilfe von Si-Evaporation und Heizen im Vakuum hergestellt werden. Für mögliche Anwendung von Pr2O3 auf Siliziumkarbid als high-k Dielektrikum wurden weiterhin Pr-Silikate und AlON untersucht. Praseodymium-Silikat konnte erfolgreich auf der SiO2 Oberfläche abgeschieden werden und gleichzeitig die Graphitisierung verhindert werden. Im Vergleich hierzu konnten sehr stabile Grenzflächen mit AlON hergestellt werden. Diese Grenzflächen bestehen hauptsächlich aus AlN mit Anteilen von Pr-Al Komplexen. Diese Schichten können als Reaktionsbarrieren zwischen Pr2O3 und SiC dienen und gleichzeitig den Band-Offset vergrößern

Evaluation of deposited silicon oxide with post-deposition annealing for gate oxide of MOS capacitors on 4H-SiC

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 재료공학부, 2018. 2. 김형준.Silicon carbide (SiC) is one of the promising materials being developed for the application of power devices. The 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) using 4H-SiC as substrate are expected to play a major role as a power semiconductor device. However, carbon clusters, which are formed in the oxidation process, increase interface states, and thus deteriorate device performance. Many researches have reported that the efficient method to remove the interfacial traps is the post-oxidation annealing (POA) using nitric oxide (NO) gas, which has become common process to remove interface traps. Although NO POA is effective on reducing interface traps, it is necessary to find the alternative and advanced methods to reduce interface traps effectively: deposition is one of them, because the most of carbon clusters are formed during oxidation process. The deposition of oxide films has been usually carried out by chemical vapor deposition (CVD) and atomic layer deposition (ALD). ALD oxide with NO post-deposition annealing (PDA) showed excellent performance was reported, but the MOSFET, which was fabricated with the ALD oxide, consisted of thin oxide less than 30 nm. However, the commercial products commonly used thicker than 50 nm. In this dissertation, oxide films thicker than 40 nm were deposited by ALD or sputtering, and then MOS capacitors were fabricated to evaluate their electrical and physical properties. And the effects of PDA conditions on the deposited oxide were also investigated. In addition, to evaluate the feasibility of oxide deposition without PDA, the oxides, which were deposited on the thermal buffer oxide, were also investigated. In order to densify the 50 nm SiO2 oxide film deposited with plasma-enhanced ALD (PEALD), the PDA was performed using Ar gas, which is an inert gas. At this time, the PDA was operated at 400, 600, 800, 1000, and 1200°C for 2 h. HF etch test and leakage current analysis showed that the oxide film was stabilized after densifying at 1000°C or higher. However, in the capacitance‒voltage (C‒V) characteristics, the densified sample at 1000°C was found to be in a less stable state, but a stable oxide film was formed only at 1200°C. In addition, the NO PDA, known to be effective at 30 nm, was conducted for 2 h at 1200°C on PEALD oxide. The C‒V hysteresis decreased significantly compared to the as-dep oxide, but the flat-band voltage (VFB) shifted significantly in the negative direction. This is because the thicker the oxide film, the greater the positive charging by nitrogen atoms. On the other hand, sputtering is a traditional physical vapor deposition (PVD) method, but it has not been often used to deposit the gate insulating films. To evaluate whether this sputtering SiO2 oxide film can be used as an insulating film, MOS capacitors with sputtered oxide were fabricated and their electrical properties and physical properties were also analyzed. N2, NH3, O2, and NO PDA were conducted to stabilize the sputtered oxide. All the samples were found to be sufficiently densified through refractive index measurement and HF etching test, and in the case of O¬2 PDA, an additional oxidation reaction occurred. As a result of the insulation property evaluation, N2 and NH3 did not have good insulation characteristics, which seems to be the result of the chemical reaction of nitrogen, increasing the leakage current. In the case of O2 and NO, they showed insulation characteristics but it was insufficient compared to thermal oxide. For the optimization of NO PDA for sputtering oxide, the 30, 60, and 90 min of NO PDAs were also investigated. As PDA time increased, VFB was negatively shifted and hysteresis decreased. As a result of normalized conductance‒frequency (GP‒ω) and Dit characteristics, the lowest interface traps were shown in the 60 min NO PDA among three conditions. Since both PEALD and sputtering use plasma, it is necessary to judge whether the plasma damage affects the substrate and interface characteristics. A passivation layer was formed through pre-oxidation before deposition, and then an oxide film was formed through PEALD and sputtering. As-deposition oxide without PDA showed poor insulating properties and large leakage current. However, pre-oxidation greatly reduced the leakage current and allowed a normal C‒V curve to be obtained. Although the leakage current is not as good as that of the thermal oxide, the overall characteristics are sufficiently improved for both PEALD and sputtering oxide. Based on these results, pre-oxidations using NO and N2O were conducted, and showed superior C‒V characteristics when using N2O and NO/O2 mixed gas. In this dissertation, whether the deposition SiO2 can be used as the gate oxide was investigated. To improve characteristics of PEALD and sputtering SiO2, post-deposition annealing and pre-oxidation were conducted. The applicability of PEALD and sputtering oxide was investigated through PDA and pre-oxidation under various conditions. If the deposition and annealing conditions were optimized, deposition oxide will have competitive enough to be used as a gate oxide for 4H-SiC MOS device.Chapter 1. Introduction 1 1.1 SiC Power Device 1 1.1.1 Power device 1 1.1.2 Conventional MOS Device 5 1.1.3 Application of SiC for power device and SiC MOS device 7 1.2. Material Properties of SiC 9 1.2.1 Structural properties 9 1.2.2 Thermal properties 12 1.2.3 Optical properties 14 1.2.4 Electrical properties 16 1.3 Gate Oxide Issue for SiC MOS Device 20 1.3.1 Conventional SiC MOSFET 20 1.3.2 The formation of defect between SiO2/SiC interface 23 Chapter 2. Literature Review 27 2.1 Fabrication Method of Gate Oxide 27 2.1.1 Thermal oxide on SiC 27 2.1.2 CVD oxide 31 2.1.3 ALD oxide 33 2.1.4 PVD oxide 35 2.2 Nitridation of SiO2 on SiC for MOS device 37 2.2.1 NO and N2O post-oxidation annealing 39 2.2.2 N2 post-oxidation annealing 43 2.2.3 Other nitridation methods 45 2.3 Basic of Device Measurement 49 2.3.1 C‒V measurement 49 2.3.2 Interface state density measurement 54 2.3.3 J‒E measurement 58 2.4 Electrical Characteristics of Gate Oxide on SiC 60 2.4.1 Thermal oxide 60 2.4.2 CVD oxide 63 2.4.3 ALD oxide 67 2.4.4 PVD oxide 73 Chapter 3. Experiment and Analysis 78 3.1 Sample Preparations 78 3.1.1 4H-SiC wafer information 78 3.1.2 Wafer cleaning process 78 3.2 Gate Oxide Deposition and Oxidation 79 3.2.1 Plasma-enhanced atomic layer deposition system 79 3.2.2 PEALD conditions of gate oxide deposition 80 3.2.3 Sputtering system and deposition condition 82 3.2.4 Dry oxidation process 83 3.3 Post-deposition annealing process 85 3.3.1 Apparatus of furnace for PDA 85 3.3.2 Ar post-deposition annealing 85 3.3.3 NO post-deposition annealing 86 3.3.4 N2, NH3, O2 Post-deposition annealing 86 3.4 MOS Capacitor Fabrication 88 3.5 Measurement and Analysis 89 3.5.1 Physical and chemical analysis of gate oxide 89 3.5.2 Electrical properties measurement of MOS capacitor 90 Chapter 4. Results and Discussions 92 4.1 Characteristics of PEALD Oxide with PDA 92 4.1.1 Effects of Ar PDA 92 4.1.2 Effects of NO PDA on 50nm SiO2 99 4.2 Characterisitcs of Sputtered Oxide with PDA 102 4.2.1 Physical and chemical properties 102 4.2.2 J‒E and oxide breakdown characteristics 108 4.2.3 C‒V and Dit characteristics 111 4.3 Analysis of Sputtered Oxide with NO PDA 117 4.3.1 C–V curve analysis 117 4.3.2 Modeling of charging in near interface traps 121 4.3.3 G–ω and Dit analysis 124 4.4 Deposited Oxide with Thermal Oxide Interlayer 127 4.4.1 PEALD oxide with dry thermal oxide 127 4.4.2 PEALD oxide with NO thermal oxide 132 4.4.3 PEALD oxide with NO/O2 and N2O thermal oxide 135 4.4.4 Sputtering Oxide with dry thermal oxide 140 4.5 Experiments Summary 144 Chapter 5. Conclusions 146 CURRICULUM VITAE 148 REFERENCES 154 LIST OF PUBLICATIONS 163 국문 초록 171Docto

Development of Schottky and MOS interfaces for SiC power devices

The very nature of the wide bandgap semiconductor silicon carbide (SiC), namely its high critical electric field, thermal conductivity and stable native oxide, silicon dioxide (SiO2), has enabled the design, fabrication and market penetration of a new generation of power devices, Schottky barrier diodes (SBDs) and metal-oxide-semiconductor fieldeffect transistors (MOSFETs), with blocking voltages from 600-1700V. Despite the successful commercial realisation of these devices, the surface of SiC and the interfaces it forms with metals (Schottky interface) and insulators (MOS interface), are still the source of reliability problems such as premature breakdown and decreased lifetime of gate oxides on SiC. The focus of this thesis lies on the exploration of passivation approaches to the Schottky interface as well as the investigation of the quality of deposited gate oxides. Firstly, an electrical and physical analysis of the impact of a proposed phosphorous pentoxide (P2O5) treatment on planar and optimised 3.3 kV JBS diodes reveals a reduction of Schottky barrier height as well as leakage current, offering a possible path to overcome the basic trade-off between on-state and off-state performance of a diode. The second part of the thesis focuses on atomic layer deposition (ALD) – deposited SiO2 layers, where a post-deposition annealing (PDA) study reveals the performance improvement when a PDA in forming gas ambient at 1100°C is carried out. This process was then successfully transferred and validated on freestanding 3C-SiC material, which successfully demonstrated the general suitability of this material for power device applications