Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

Transient dynamics of a superconducting nonlinear oscillator

We investigate the transient dynamics of a lumped-element oscillator based on a dc superconducting quantum interference device (SQUID). The SQUID is shunted with a capacitor forming a nonlinear oscillator with resonance frequency in the range of several GHz. The resonance frequency is varied by tuning the Josephson inductance of the SQUID with on-chip flux lines. We report measurements of decaying oscillations in the time domain following a brief excitation with a microwave pulse. The nonlinearity of the SQUID oscillator is probed by observing the ringdown response for different excitation amplitudes while the SQUID potential is varied by adjusting the flux bias. Simulations are performed on a model circuit by numerically solving the corresponding Langevin equations incorporating the SQUID potential at the experimental temperature and using parameters obtained from separate measurements characterizing the SQUID oscillator. Simulations are in good agreement with the experimental observations of the ringdowns as a function of applied magnetic flux and pulse amplitude. We observe a crossover between the occurrence of ringdowns close to resonance and adiabatic following at larger detuning from the resonance. We also discuss the occurrence of phase jumps at large amplitude drive. Finally, we briefly outline prospects for a readout scheme for superconducting flux qubits based on the discrimination between ringdown signals for different levels of magnetic flux coupled to the SQUID.Comment: 15 pages, 9 figure

Transmissor RF de elevado rendimento com duas entradas digitais para sistemas 5G

In recent years, there has been a need to increase the capacity and speed of information transmission, so the communication signals used in mobile communications have been improved to meet the expectations. This will be even more significant in future 5G systems, since due to the high expansion of wireless devices, current 4G systems are starting to push their limits, where only small improvements can be achieved. Which complicates the design of transmitters, since these new signals have a wider bandwidth and a large variation between their average and peak value, causing amplifiers to operate most of the time in a zone where they are not as efficient. For this reason, amplifier architectures not only aim to have high efficiency when operating at maximum signal excursion, but also to increase efficiency in the zone where they will operate most of the time. For this purpose, there are architectures based on supply voltage modulation and load modulation to improve the efficiency at lower powers. This work addresses load modulation architectures, where Doherty and Chireix are the most prominent. In addition, with the increase in digital signal processing capabilities, new amplification architectures based on the load modulation technique have recently been proposed, but instead of using only one RF input, they use two independent digitally controlled inputs. This dissertation aims at implementing a Doherty-Chireix amplifier with two digital inputs to achieve efficient amplification for the 1.7 to 2.4GHz frequency band. In the end it was possible to design and implement a Doherty-Chireix power amplifier, with 700MHz bandwidth, with a gain between 13.9-11.3dB, a maximum power of 45dBm, a PAE of over 60% and peak-to-average power ratio between 5.2-4.1dB.Nos últimos anos, tem havido uma necessidade de aumentar a capacidade e velocidade de transmissão de informação, deste modo os sinais de comunicação utilizados nas comunicações móveis têm evoluído por forma a corresponder as expectativas. Tal será ainda mais significativo nos futuros sistemas 5G, já que devido à elevada expansão de dispositivos sem fio, os atuais sistemas 4G estão a começar a atingir os seus limites, onde apenas pequenas melhorias podem ser alcançadas. Isto vem complicar o projeto dos transmissores, uma vez que estes novos sinais apresentam uma maior largura de banda e uma grande variação entre o seu valor médio e de pico, fazendo com que os amplificadores operem na maior parte do tempo numa zona em que não são tão eficientes. Por esta razão, as arquiteturas de amplificação nos dias de hoje não só visam ter um grande rendimento quando operam com a máxima excursão de sinal, mas também o aumento do rendimento na zona onde irão operar a maior parte do tempo. Nesse sentido existem arquiteturas baseadas em modelação de tensão de alimentação e modelação de carga de modo a melhorar a eficiência a potências mais baixas. Neste trabalho são abordadas arquiteturas de modulação de carga, onde Doherty e Chireix são as que mais se destacam. Para além disso, com o aumento da capacidade de processamento digital de sinal, recentemente foram propostas novas arquiteturas de amplificação que se baseiam nestas técnicas, mas em vez de utilizar apenas uma entrada de RF, usam duas entradas independentes controladas digitalmente. Esta dissertação visa a implementação de um amplificador Doherty-Chireix com duas entras digitais de modo a obter uma amplificação eficiente para uma banda de frequências de 1.7 a 2.4GHz. No final foi possível projetar e implementar um amplificador de potência Doherty-Chireix, com 700MHz de largura de banda, com um ganho compreendido entre 13.9-11.3dB, potência máxima de 45dBm, uma PAE superior a 60% e peak-to-average power ratio entre 5.2-4.1dB.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

DESIGN OF CLASS F-BASED DOHERTY POWER AMPLIFIER FOR S-BAND APPLICATIONS

Modern RF and millimeter-wave communication links call for high-efficiency front end systems with high output power and high linearity to meet minimum transmission requirements. Advanced modulation techniques, such as orthogonal frequency-division multiplexing (OFDM) require a large power amplifier (PA) dynamic range due to the high peak-to-average power ratio (PAPR). This thesis provides the analysis, design, and experimental verification of a high-efficiency, high-linearity S-band Doherty power amplifier (DPA) based on the Class F PA. Traditional Class F PAs use harmonically tuned output matching networks to obtain up to 88.4% power-added efficiency (PAE) theoretically, however the amplifier experiences poor linearity performance due to switched mode operation, typically yielding less than 30dB C/I ratio [1]. The DPA overcomes this linearity limitation by using an auxiliary amplifier to boost output power when the amplifier is subject to a high input power due to its limited conduction cycle. The DPA also provides improved saturated output power back-off performance to maintain high PAE during operation. The DPA presented in this thesis optimizes PAE while maintaining linearity by employing harmonically tuned Class F amplifier topology on a primary and an auxiliary amplifier. A Class F PA is first designed and fabricated to optimize output network linearity – this is followed by a DPA design based on the fabricated Class F PA. A GaN HEMT Class F PA and DPA operating at 2.2GHz are implemented with the PAs measuring 40% and 45% PAE respectively while maintaining a 30dB carrier-to-intermodulation (C/I) ratio on a two-tone test. The PAE is characterized at maximum 21dBm input power per tone and 20MHz tone spacing. When subject to a single 24dBm continuous wave input tone, the Class F PA and DPA output 37dBm and 35.5dBm respectively. The PAs presented in the thesis provide over 30dB C/I ratio up to 21dBm input tones while maintaining over 40% PAE suitable for base station applications

Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology

Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome. This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band

Reconfigurable RF Front End Components for Multi-Radio Platform Applications

The multi-service requirements of the 3G and 4G communication systems, and their backward compatibility requirements, create challenges for the antenna and RF front-end designs with multi-band and wide-band techniques. These challenges include: multiple filters, which are lossy, bulky, and expensive, are needed in the system; device board size limitation and the associated isolation problems caused by the limited space and crowd circuits; and the insertion loss issues created by the single-pole-multi-through antenna switch. As will be shown, reconfigurable antennas can perform portions of the filter functions, which can help solve the multiple filters problem. Additionally, reconfigurable RF circuits can decrease the circuit size and output ports, which can help solve board size limitation, and isolation and antenna switch insertion loss issues. To validate the idea that reconfigurable antennas and reconfigurable RF circuits are a viable option for multi-service communication system, a reconfigurable patch antenna, a reconfigurable monopole antenna, and a reconfigurable power amplifier (PA) have been developed. All designs adapt state-of-the-art techniques. For the reconfigurable antenna designs, an experiment demonstrating its advantages, such as jamming signal resistance, has been performed. Reconfigurable antennas provide a better out-ofoperating- band noise performance than the multi-band antennas design, decreasing the need for filters in the system. A full investigation of reconfigurable antennas, including the single service reconfigurable antenna, the mixed signal service reconfigurable antenna, and the multi-band reconfigurable antenna, has been completed. The design challenges, which include switches investigation, switches integration, and service grouping techniques, have been discussed. In the reconfigurable PA portion, a reconfigurable PA structure has first been demonstrated, and includes a reconfigurable output matching network (MN) and a reconfigurable die design. To validate the proposed reconfigurable PA structure, a reconfigurable PA for a 3G cell phone system has been designed with a multi-chip module technique. The reconfigurable PA structure can significantly decrease the real-estate, cost, and complexity of the PA design. Further, by decreasing the number of output ports, the number of poles for the antenna switch will be decreased as well, leading to an insertion loss decrease

24GHz CMOS direct downconversion receiver front-end and VCO design

Because of advancements in RF CMOS circuits, devices, and passive elements in the last decade, it has become possible to develop a RF system-on-chip (SoC) that integrates RF, analog and digital circuits completely. Direct downconversion, or zero-IF downconversion architecture, shows an advantage over traditional superheterodyne architectures, because it eliminates the image rejection filter and IF filter, and employs only one local oscillator (LO), which reduces the receiver size and power dissipation significantly. For this reason, direct downconversion has drawn more and more attention recently in various wireless applications. However, it also presents some design challenges like flicker noise, DC offsets, even-order distortion, and I/Q mismatches. In this work, a thorough noise analysis and a comprehensive study of the noise mechanism of the low noise amplifier of CMOS direct downconversion receivers (DCR) is given. Also addressed is the design of a cross-coupled LC voltage-controlled oscillator (VCO). For the low noise amplifier, which presents major noise contribution to the DCR front-end, an optimization technique which employs both a parallel capacitance and an inter-stage inductor is proposed. The addition of this capacitance helps keep the active device relatively small, and the analysis on the effects of the inter-stage inductor shows that it helps boost gain of the LNA at the desired operation frequency of 2.4GHz, and offers a lower noise figure. In order to achieve direct downconversion, both a passive switching mixer and an active double-balanced mixer are presented. The passive switching mixer helps solve the problem of flicker noise, but suffers power loss, while the double-balanced architecture helps relieve the problems of DC offset and second-order distortion. The last part of this presentation is about a partially tunable CMOS LC-VCO which achieves good phase noise performance at the cost of smaller tuning range. It uses on-chip spiral inductors and junction varactors in the resonant LC-tank. The presented building blocks can be used for a low-power, low-voltage DCR front-end for 802.11b/g applications. It is concluded that direct downconversion architecture can find its use in low-power, low-cost 802.11b and Bluetooth applications should the circuit design make use of the optimization techniques addressed in this work

EMBEDDED POWER ACTIVE CONTACT LENS

This thesis designed and fabricated an active contact lens that notifies the user during the detection of an external wireless signal. The lens contained a printed antenna to communicate with a 2.4GHz system and provide inductive charging operating at 13.56 MHz. The lens utilizes a CBC005 5µAh thin film battery by Cymbet as a power source. A custom IC was designed using the On Semiconductor CMOS C5 0.6 µm process to manage the battery and drive the display. A printed single element display using electrochromic ink was chosen as it is able to indicate the user when activated while staying transparent. Lastly, this thesis analyzes the material properties of the chosen substrate for it clearness, flexibility, and biocompatibility to determine its suitability as a contact lens material

Ultra-low power radio transceiver for wireless sensor networks

The objective of this thesis is to present the design and implementation of ultra-low power radio transceivers at microwave frequencies, which are applicable to wireless sensor network (WSN) and, in particular, to the requirement of the Speckled Computing Consortium (or SpeckNet). This was achieved through quasi-MMIC prototypes and monolithic microwave integrated circuit (MMIC) with dc power consumption of less than 1mW and radio communication ranges operating at least one metre. A wireless sensor network is made up of widely distributed autonomous devices incorporating sensors to cooperatively monitor physical environments. There are different kinds of sensor network applications in which sensors perform a wide range of activities. Among these, a certain set of applications require that sensor nodes collect information about the physical environment. Each sensor node operates autonomously without a central node of control. However, there are many implementation challenges associated with sensor nodes. These nodes must consume extremely low power and must communicate with their neighbours at bit-rates in the order of hundreds of kilobits per second and potentially need to operate at high volumetric densities. Since the power constraint is the most challenging requirement, the radio transceiver must consume ultra-low power in order to prolong the limited battery capacity of a node. The radio transceiver must also be compact, less than 5×5 mm2, to achieve a target size for sensor node and operate over a range of at least one metre to allow communication between widely deployed nodes. Different transceiver topologies are discussed to choose the radio transceiver architecture with specifications that are required in this project. The conventional heterodyne and homodyne topologies are discussed to be unsuitable methods to achieve low power transceiver due to power hungry circuits and their high complexity. The super-regenerative transceiver is also discussed to be unsuitable method because it has a drawback of inherent frequency instability and its characteristics strongly depend on the performance of the super-regenerative oscillator. Instead, a more efficient method of modulation and demodulation such as on-off keying (OOK) is presented. Furthermore, design considerations are shown which can be used to achieve relatively large output voltages for small input powers using an OOK modulation system. This is important because transceiver does not require the use of additional circuits to increase gain or sensitivity and consequently it achieves lower power consumption in a sensor node. This thesis details the circuit design with both a commercial and in-house device technology with ultra-low dc power consumption while retaining adequate RF performance. It details the design of radio building blocks including amplifiers, oscillators, switches and detectors. Furthermore, the circuit integration is presented to achieve a compact transceiver and different circuit topologies to minimize dc power consumption are described. To achieve the sensitivity requirements of receiver, a detector design method with large output voltage is presented. The receiver is measured to have output voltages of 1mVp-p for input powers of -60dBm over a 1 metre operating range while consuming as much as 420μW. The first prototype combines all required blocks using an in-house GaAs MMIC process with commercial pseudomorphic high electron mobility transistor (PHEMT). The OOK radio transceiver successfully operates at the centre frequency of 10GHz for compact antenna and with ultra-low power consumption and shows an output power of -10.4dBm for the transmitter, an output voltage of 1mVp-p at an operating range of 1 metre for the receiver and a total power consumption of 840μW. Based on this prototype, an MMIC radio transceiver at the 24GHz band is also designed to further improve the performance and reduce the physical size with an advanced 50nm gate-length GaAs metamorphic high electron mobility transistor (MHEMT) device technology