A Network Structure for Diagnosis of Four Types of Faults in Reed-Muller Canonical Circuits

In this paper, a new network structure and its associated universal test set, independent of the circuit function, and dependent only on the number of function variables, with good fault diagnosing capabilities have been proposed for single stuck-at, double stuck-at, AND-bridging and OR-bridging faults in Exclusive-OR Sum of Products (ESOP) Reed-Muller Canonical (RMC) circuits

Canonical multi-valued input Reed-Muller trees and forms

There is recently an increased interest in logic synthesis using EXOR gates. The paper introduces the fundamental concept of Orthogonal Expansion, which generalizes the ring form of the Shannon expansion to the logic with multiple-valued (mv) inputs. Based on this concept we are able to define a family of canonical tree circuits. Such circuits can be considered for binary and multiple-valued input cases. They can be multi-level (trees and DAG's) or flattened to two-level AND-EXOR circuits. Input decoders similar to those used in Sum of Products (SOP) PLA's are used in realizations of multiple-valued input functions. In the case of the binary logic the family of flattened AND-EXOR circuits includes several forms discussed by Davio and Green. For the case of the logic with multiple-valued inputs, the family of the flattened mv AND-EXOR circuits includes three expansions known from literature and two new expansions

LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

Generalized Inclusive Forms — New Canonical Reed-Muller Forms Including Minimum ESOPs

Reed-Muller (AND/EXOR) expansions play an important role in logic synthesis and circuit design by producing economical and highly-testable implementations of Boolean functions [3–6]. The range of Reed-Muller expansions include canonical forms, i.e. expansions that create unique representations of a Boolean function. Several large families of canonical forms: fixed polarity Reed-Muller forms (FPRMs), generalized Reed-Muller forms (GRMs), Kronecker forms (KROs), and pseudo- Kronecker forms (PKROs), referred to as the Green/Sasao hierarchy, have been described [7–9]. (See Fig. 1 for a settheoretic relationship between these families.

Fault testing quantum switching circuits

Test pattern generation is an electronic design automation tool that attempts to find an input (or test) sequence that, when applied to a digital circuit, enables one to distinguish between the correct circuit behavior and the faulty behavior caused by particular faults. The effectiveness of this classical method is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. This work address the quantum process validation problem by considering the quantum mechanical adaptation of test pattern generation methods used to test classical circuits. We found that quantum mechanics allows one to execute multiple test vectors concurrently, making each gate realized in the process act on a complete set of characteristic states in space/time complexity that breaks classical testability lower bounds.Comment: (almost) Forgotten rewrite from 200

AN EXTENDED GREEN-SASAO HIERARCHY OF CANONICAL TERNARY GALOIS FORMS AND UNIVERSAL LOGIC MODULES

A new extended Green-Sasao hierarchy of families and forms with a new sub-family for many-valued Reed-Muller logic is introduced. Recently, two families of binary canonical Reed-Muller forms, called Inclusive Forms (IFs) and Generalized Inclusive Forms (GIFs) have been proposed, where the second family was the first to include all minimum Exclusive Sum-Of-Products (ESOPs). In this paper, we propose, analogously to the binary case, two general families of canonical ternary Reed-Muller forms, called Ternary Inclusive Forms (TIFs) and their generalization of Ternary Generalized Inclusive Forms (TGIFs), where the second family includes minimum Galois Field Sum-Of-Products (GFSOPs) over ternary Galois field GF(3). One of the basic motivations in this work is the application of these TIFs and TGIFs to find the minimum GFSOP for many-valued input-output functions within logic synthesis, where a GFSOP minimizer based on IF polarity can be used to minimize the many-valued GFSOP expression for any given function. The realization of the presented S/D trees using Universal Logic Modules (ULMs) is also introduced, whereULMs are complete systems that can implement all possible logic functions utilizing the corresponding S/D expansions of many-valuedShannon and Davio spectral transforms.   

Testing a Quantum Computer

The problem of quantum test is formally addressed. The presented method attempts the quantum role of classical test generation and test set reduction methods known from standard binary and analog circuits. QuFault, the authors software package generates test plans for arbitrary quantum circuits using the very efficient simulator QuIDDPro[1]. The quantum fault table is introduced and mathematically formalized, and the test generation method explained.Comment: 15 pages, 17 equations, 27 tables, 8 figure

New minimization method of logical functions in polynomial set-theoretical format. 1. Generalized rules of conjuncterms simplification

A generalized simplify rules of conjuncterms in polynomial set-theoretical format is considered. These rules are based on the proposed theorems for different initial transform condition of pair conjuncterms where hamming distance between them can be arbitrary. These rules may be useful to minimize in polynomial set-theoretical format of arbitrary logic functions of n variables. Advantages of the proposed rules are illustrated by the examples.Рассмотрены обобщенные правила упрощения конъюнктермов в полиномиальном теоретико-множественном формате, основанные на предложенных теоремах для разных начальных условий преобразования пары конъюнктермов, хеммингово расстояние между которыми может быть произвольным. Упомянутые правила могут быть полезными для минимизации в полиномиальном теоретико-множественном формате произвольных логических функций от n переменных. Преимущества предложенных правил проиллюстрированы примерами.Розглянуто узагальнені правила спрощення кон’юнктермів у поліноміальному теоретико-множинному форматі, які ґрунтуються на запропонованих теоремах для різних початкових умов перетворення пари кон’юнктермів, геммінгова відстань між якими може бути довільна. Зазначені правила можуть бути корисні для мінімізації у поліноміальному теоретико-множинному форматі довільних логічних функцій від n змінних. Переваги запропонованих правил проілюстровано прикладами

A New Method of Minimization of Logical Functions in the Polynomial Set-theoretical Format. 2. Minimization of Complete and Incomplete Functions

A new minimization method of the logic functions of n variables in the polynomial set-theoretical format is considered. The method is based on the splitting procedure of the given minterms and on the generalized of the set-theoretical simplify rules of the conjuncterms of different ranks. The advantages of the method are illustrated by the examples.Рассмотрен новый метод минимизации логических функций от n переменных в полиномиальном теоретико-множественном формате, основанный на процедуре расцепления заданных минтермов и обобщенных теоретико-множественных правилах упрощения конъюнктермов разных рангов. Преимущества метода иллюстрируют примеры.Розглянуто новий метод мінімізації логічних функцій від n змінних у поліноміальному теоретико-множинному форматі, що ґрунтується на процедурі розчеплення заданих мінтермів та узагальнених теоретико-множинних правилах спрощення кон’юнктермів різних рангів. Переваги методу ілюструють приклади