Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Fathianathan, Mervyn; Committee Member: Lim, Sung Kyu; Committee Member: Peterson, Andrew; Committee Member: Tentzeris, Mano

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

Process Characterization and Optimization of Roll-to-Roll Plasma Chemical Vapor Deposition for Graphene Growth

Large-scale production of graphene and other nanostructures remains a hindrance to their adoption in the semiconductor and materials manufacturing industries. The main purpose of this thesis is to develop an efficient and scalable technique for depositing graphene on various flexible substrates. Hence, a custom-built roll-to-roll capacitively coupled plasma chemical vapor system for deposition of graphene on flexible substrates is thoroughly described in this work. Graphene quality on Cu foil has been optimized for a roll-to-roll process using statistical optimization methods. Since graphene quality and uniformity depend on plasma input parameters, such as plasma power, gas pressure, and the gas mixture used, effects of input parameters have been explored to maximize graphene quality, as quantified by Raman spectroscopy using the ID/IG intensity ratio. Furthermore, in situ optical emission spectroscopy (OES) has been developed and utilized to determine the effects of several plasma species on graphene growth and quality. OES results demonstrate that graphene quality on Cu foil increases with CH radical emission; however, O and H atoms, C2 and CN radicals, and Ar+ ion all negatively correlate to graphene quality. Results aid in developing a conceptual model for a graphene growth mechanism that indicates the adverse impact of ion bombardment on graphene quality in the low-frequency capacitively coupled plasma. However, the existence of active carbon species in the plasma, such as CH radical, accelerates the growth process and leads to moderate-quality graphene deposition on Cu foil at web speeds reaching as high as 1 m/min. Nevertheless, graphene quality measured from Raman spectroscopy declines significantly with increased Cu foil velocity (web speed) in the roll-to-roll process, inducing a critical limitation in current production rates for roll-to-roll CVD nonmanufacturing techniques. With the aid of heat transfer modeling of the moving foil, we show that the graphene quality decrease is primarily due to Cu foil temperature decline with increased web speed. The Cu foil temperature distribution is determined both experimentally and numerically during roll-to-roll graphene growth as a function of web speed, plasma power and plasma length. The maximum Cu foil temperature in the plasma rises with increased plasma power due to increased heating from the plasma. However, the maximum Cu foil temperature decreases with increased web speed caused by higher heat advection by the moving foil. In addition, shortening the plasma slit (by decreasing the electrodes length) cools the Cu foil temperature and diminishes its temperature uniformity in the plasma region. Consequently, graphene crystallization, identified using Raman spectroscopy, improves with higher Cu foil temperatures. As a result, an optimum condition is defined by raising the plasma power, lowering the web speed and increasing the plasma region length, which consistently produces high-quality graphene on Cu foil. The throughput of graphene production can be increased by utilizing Ni foil as a substrate since carbon solubility in Ni is higher than in Cu. Thus, the effects of web speed and plasma power on Ni foil temperature distribution are evaluated during graphene deposition in the roll-to-roll process. Furthermore, the Ni foil cooling rate, which strongly affects carbon atom segregation from Ni after the growth process, is derived from the heat transfer model. Plasma power has negligible effects on the cooling rate, whereas the web speed has a significant impact on the cooling rate. Consequently, graphene has comparable quality at different plasma powers, whereas web speed controls graphene quality, particularly with regards to uniformity and thickness. Our work highlights the benefits of using Ni foil in a roll-to-roll process for graphene deposition at higher web speeds and lower substrate temperatures, rather than using Cu foil, which requires significantly more substrate heating. Plasma plays a crucial role in heating the foil for graphene deposition in the roll-to-roll process, without the need of a supplemental heating source. Thus, accurate measurement of the translational gas temperature in the plasma is vital, since gas temperature strongly influences the foil temperature distribution, which, in turn, affects graphene growth kinetics. Optical emission spectroscopy (OES) is used to measure the rotational temperatures of N2 + (B-X), CN (B-X) and H2 (d3Πu → a3Σg +), and to determine accurate translational gas temperatures. Power dissipation in the plasma is also measured to understand gas temperature variation for the experimental input conditions. Thus, the effects of plasma power, gas pressure and the addition of nitrogen (N2), oxygen (O2) and methane (CH4) gases on power dissipation and gas temperature in a hydrogen (H2) plasma are assessed. The rotational temperatures measured from the gas species have different values due to the non-equilibrium nature of the plasma. Of the gases measured, the rotational temperature of N2 + is most accurate in representing the translational gas temperature. These results improve the understanding and control of the thermochemical environment for carbon nanostructure growth in the plasma chemical vapor deposition processes. Graphene quality significantly depends on gas pressure since our plasma roll-to-roll system is sustained by a capacitively coupled plasma that operates in two modes, depending on the gas pressure and discharge gap. The modes are identified as alpha and gamma modes, and are sustained by volume ionization and secondary electron emission processes, respectively. Up to our knowledge, the presence of both modes at 80 kHz plasma frequency has not previously been reported. Thus, a detailed characterization of argon plasma is attempted to determine the underlying plasma physics of the low-frequency plasma. Due to strong ion bombardment on the electrodes, the gamma mode coexists with the alpha mode, resulting in a hybrid mode. The voltage square waveform is found to play an important role in sustaining this hybrid mode. The hybrid mode exists at low gas pressures of 5.5 and 9.5 mbar in the plasma set power ranges from 300 to 1100 W. However, the plasma at 13.8 mbar gas pressure transforms from hybrid to gamma mode when the plasma set power is beyond 750 W due to increased secondary electron emission processes. The emission spectra measured from optical emission spectroscopy reveal the presence of non-Ar species in the gamma mode, such as H, CH, and C2. These species are sputtered from the graphite electrodes by ion bombardment to produce secondary electrons that sustain the gamma discharge. Results show the possibility of sustaining the hybrid mode at a low plasma frequency using a tailored waveform. As a results of these plasma characterization tools, we report a continuous and rapid rollto- roll deposition of thin graphite film on Cu foil. The composition of the Ar/H2/CH4/N2/O2 plasma plays significant role in the successful direct growth of the thin graphite film on copper foil. Optical emission spectroscopy is used to characterize the plasma during graphite synthesis and show that the addition of N2 enhances the plasma reactivity, and O2 was found to increase the deposition rate of the graphite film. The film was characterized by Raman spectroscopy, scanning electron microscopy (SEM), transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS). The described large-scale graphite production can produce a graphite-Cugraphite structure or uniform thin graphite films for thermal management applications in electronics devices. Graphene growth optimization, substrate thermal analysis, and plasma characterizations are used to control graphene mass-production in a custom-built roll-to-roll plasma CVD system. These techniques are addressed to provide a route for nanomanufacturing of graphene and graphite on Cu and Ni foils. These methods aid in understanding the correlations between process conditions and graphene quality, as well as the interactions between the plasma and the substrate, to yield high-throughput production of high-quality graphene. The procedure outlined here can be applied to efficiently scale-up the production of other micro- and nanomaterials

Special Topics in Information Technology

This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2020-21 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

Special Topics in Information Technology

This open access book presents thirteen outstanding doctoral dissertations in Information Technology from the Department of Electronics, Information and Bioengineering, Politecnico di Milano, Italy. Information Technology has always been highly interdisciplinary, as many aspects have to be considered in IT systems. The doctoral studies program in IT at Politecnico di Milano emphasizes this interdisciplinary nature, which is becoming more and more important in recent technological advances, in collaborative projects, and in the education of young researchers. Accordingly, the focus of advanced research is on pursuing a rigorous approach to specific research topics starting from a broad background in various areas of Information Technology, especially Computer Science and Engineering, Electronics, Systems and Control, and Telecommunications. Each year, more than 50 PhDs graduate from the program. This book gathers the outcomes of the thirteen best theses defended in 2020-21 and selected for the IT PhD Award. Each of the authors provides a chapter summarizing his/her findings, including an introduction, description of methods, main achievements and future work on the topic. Hence, the book provides a cutting-edge overview of the latest research trends in Information Technology at Politecnico di Milano, presented in an easy-to-read format that will also appeal to non-specialists

Statistical static timing analysis considering process variations and crosstalk

Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analysis results. In addition, intra-die process variations are spatially correlated due to pattern dependencies in the manufacturing process. Any statistical static timing analysis (SSTA) tool is incomplete without a model for signal crosstalk, as critical path delays can increase or decrease depending on the switching of capacitively coupled nets. The coupled signal timing in turn depends on the process variations. This work describes an SSTA tool that models signal crosstalk and spatial correlation in intra-die process variations, along with gradients and inter-die variations

Crosstalk Noise Analysis for Nano-Meter VLSI Circuits.

Scaling of device dimensions into the nanometer process technology has led to a considerable reduction in the gate delays. However, interconnect delays have not scaled in proportion to gate delays, and global-interconnect delays account for a major portion of the total circuit delay. Also, due to process-technology scaling, the spacing between adjacent interconnect wires keeps shrinking, which leads to an increase in the amount of coupling capacitance between interconnect wires. Hence, coupling noise has become an important issue which must be modeled while performing timing verification for VLSI chips. As delay noise strongly depends on the skew between aggressor-victim input transitions, it is not possible to a priori identify the victim-input transition that results in the worst-case delay noise. This thesis presents an analytical result that would obviate the need to search for the worst-case victim-input transition and simplify the aggressor-victim alignment problem significantly. We also propose a heuristic approach to compute the worst-case aggressor alignment that maximizes the victim receiver-output arrival time with current-source driver models. We develop algorithms to compute the set of top-k aggressors in the circuit, which could be fixed to reduce the delay noise of the circuit. Process variations cause variability in the aggressor-victim alignment which leads to variability in the delay noise. This variability is modeled by deriving closed-form expressions of the mean, the standard deviation and the correlations of the delay-noise distribution. We also propose an approach to estimate the confidence bounds on the path delay-noise distribution. Finally, we show that the interconnect corners obtained without incorporating the effects of coupling noise could lead to significant errors, and propose an approach to compute the interconnect corners considering the impact of coupling noise.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/64663/1/gravkis_1.pd

Sincronização em sistemas integrados a alta velocidade

Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.Distributing a the clock simultaneously everywhere (low skew) and periodically everywhere (low jitter) in high-performance Integrated Circuits (ICs) has become an increasingly di cult and time-consuming task, due to technology scaling. As transistor dimensions shrink and more functionality is packed into an IC, clock precision becomes increasingly a ected by Process, Voltage and Temperature (PVT) variations. This thesis addresses the problem of clock uncertainty in high-performance ICs, in order to determine the limits of the synchronous design paradigm. In pursuit of this main goal, this thesis proposes four new uncertainty models, with di erent underlying principles and scopes. The rst model targets uncertainty in static CMOS inverters. The main advantage of this model is that it depends only on parameters that can easily be obtained. Thus, it can provide information on upcoming constraints very early in the design stage. The second model addresses uncertainty in repeaters with RC interconnects, allowing the designer to optimise the repeater's size and spacing, for a given uncertainty budget, with low computational e ort. The third model, can be used to predict jitter accumulation in cascaded repeaters, like clock trees or delay lines. Because it takes into consideration correlations among variability sources, it can also be useful to promote oorplan-based power and clock distribution design in order to minimise jitter accumulation. A fourth model is proposed to analyse uncertainty in systems with multiple synchronous domains. It can be easily incorporated in an automatic tool to determine the best topology for a given application or to evaluate the system's tolerance to power-supply noise. Finally, using the proposed models, this thesis discusses clock precision trends. Results show that limits in clock precision are ultimately imposed by dynamic uncertainty, which is expected to continue increasing with technology scaling. Therefore, it advocates the search for solutions at other abstraction levels, and not only at the physical level, that may increase system performance with a smaller impact on the assumptions behind the synchronous design paradigm